
PRELIMINARY
XRT79L71
252
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
RxOHInd/RxGapClk
C6
O
Receive Overhead Bit Indicator Output/Receive Gap-Clock Output:
The exact function of this output pin depends upon whether the XRT79L71
has been configured to operate in the Gapped-Clock Mode or Not.
Non-Gapped Clock Mode - RxOHInd:
This output pin will pulse "High", for one RxClk period, coincident to whenever
the Receive Payload Data Output Interface block outputs an overhead bit via
the RxSer output pin. This output pin will be held "Low" at all other times. The
purpose of this output pin is to alert the System-Side Terminal Equipment that
the current bit (e.g., the one that is currently residing on the RxSer output pin)
is an overhead bit and should not be processed by the System-Side Terminal
Equipment.
The XRT79L71 will update output signal upon the rising edge of RxClk.
Therefore, the user is advised to design or configure the System-Side Termi-
nal Equipment to sample this signal along with the data on the RxSer output
pin on the falling edge of the RxClk signal.N
NOTE: For DS3 Applications, this output pin is only active in the RxOHInd role
if the Receive Payload Data Output Interface block has been
configured to operate in the Serial Mode. This output pin will be held
"Low" at all times.
Gapped Clock Mode - RxGapClk:
If the XRT79L71 has been configured to operate in the Gapped-Clock Mode,
then this particular output pin will function as a payload bit output clock signal.
In other words, in this mode, the Receive Payload Output Interface block will
only generate a clock pulse via this output pin coincident to whenever it out-
puts a payload bit via the RxSer output pin. The Receive Payload Data Output
Interface block will NOT generate a clock edge via this output pin coincident to
whenever it outputs an overhead bit via the RxSer output pin. As a conse-
quence, there will be gaps within this particular clock output signal, hence the
name Gapped Clock Mode.
If the XRT79L71 is configured to operate in the Gapped Clock Mode, then
they must design or configure the System-Side Terminal Equipment to sample
and latch the RxSer data upon the falling edge of the RxOHInd/RxGapClk
clock signal.
RxFrame
B6
O
Receive Payload Data Output Interface - Receive Start of Frame Output
Indicator:
The exact behavior of this output pin depends upon whether the XRT79L71
has been configured to operate in the Serial or in the Nibble-Parallel Mode, as
described below.
Serial Mode Operation
The Receive Payload Data Output Interface block will pulse this output pin
"High" for one RxCLK period coincident to whenever it outputs the very first bit
of a new DS3 frame via the RxSer output pin. This output pin will remain
"Low" at all other times.
Nibble-Parallel Mode Operation
The Receive Payload Data Output Interface block will pulse this output pin
"High" for one RxCLK or Nibble-Period coincident to whenever it outputs the
very first nibble of a new DS3 frame via the RxNib[3:0] output pins. This out-
put pin will remain "Low" at all other times.
TABLE 34: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT
INTERFACE BLOCK
SIGNAL NAME
PIN/BALL #TYPE
DESCRIPTION