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PRELIMINARY
XRT79L71
224
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NOTE: For instructions on how to read out these "Performance Monitor" Registers please see Section 2.5. 4.3.2.11
DETECTING FRAMING BIT ERRORS
The Receive DS3/E3 Framer block has the responsibility for detecting and flagging the occurrences of Framing
(e.g., F or M) bit errors as described below.
While the Receive DS3 Framer block is operating in the Frame Maintenance Mode, it will continue to check for
valid F and M bits within the incoming DS3 data-stream. If the Receive DS3 Framer block detects any errors in
the F or M bits, then it will do the following.
Increment the PMON Framing Bit/Byte Error Count Register once for each DS3 frame that is determined to
contain an erred F or M bits. The PMON Framing Bit/Byte Error Count Register is located at Address =
0x1152/0x1153. The bit-format of these registers is presented below.
NOTE: For instructions on how to read out these "Performance Monitor" Registers please see Section 2.5. 4.3.2.12
Receive DS3/E3 Framer Block Interrupts
4.3.3
RECEIVE LAPD CONTROLLER BLOCK
The Receive LAPD Controller Block is the four functional block within the Receive Direction of the XRT79L71
that we will discuss for Clear-Channel Framer Applications. Figure 95 presents an illustration of the Receive
Direction circuitry whenever the XRT79L71 has been configured to operate in the DS3 Clear-Channel Framer
Mode, with the Receive LAPD Controller block highlighted.
PMON FEBE Event Count Register - LSB (Address = 0x1157)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_FEBE_Event_Count_Lower_Byte[7:0]
RUR
0
PMON Framing Bit/Byte Error Count Register - MSB (Address = 0x1152)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_Framing_Bit/Byte_Error_Count_Upper_Byte[7:0]
RUR
0
PMON Framing Bit/Byte Error Count Register - LSB (Address = 0x1153)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_Framing_Bit/Byte_Error_Count_Lower_Byte[7:0]
RUR
0