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XRT79L71
PRELIMINARY
509
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
This setting will configure the Transmit DS3/E3 Framer block to respond to occurrence of EM byte errors as
detected by the corresponding, Near-End Receive DS3/E3 Framer block as depicted above in Figure 239 and
6.2.6.5
Setting the Payload-Type Bit-fields within the outbound E3 Data-stream
6.2.6.6
User Control over the GC Byte within the outbound E3 data-stream
6.2.6.7
User Control over the NR Byte within the outbound E3 data-stream
6.2.6.8
Setting the Transmit E3 Framer Block Timing Reference
As a user designs their system, they ultimately have to decide whether their system is going to be configured to
operate in either the Local-Timing Mode (e.g., where the timing source for the Transmit [or outbound] Direction
traffic is derived from a "local" [or in-system] clock source) or in the Loop-Timing Mode (e.g., where the timing
source for the Transmit [or outbound] Direction traffic is derived from the "remote terminal equipment's" clock
source. The XRT79L71 can be configured to support either of these applications.
In all, the XRT79L71 supports the following three (3) different Timing Reference Modes.
Local-Timing/Asynchronous
Local-Timing/TxFrameRef
Loop-Timing
6.2.6.8.1
Local-Timing/Asynchronous Mode
If the XRT79L71 is configured to operate in the Local-Timing/Asynchronous Mode, then the following are true.
The Transmit E3 Framer block will use the clock signal that is applied to the TxInClk input pin as its timing
source, for generating and transmitting the outbound E3 traffic to the remote terminal equipment.
E3 Frame Generation (e.g., the instant whenever the Transmit E3 Framer block begins to generate and
transmit a new E3 frame) is asynchronous with respect to any externally supplied clock signal to the
XRT79L71.
Configuring the XRT79L71 to operate in the Local-Timing/Asynchronous Mode
The XRT 79L71 can be configured to operate in the "Local-Timing/Asynchronous" Mode by setting Bits 1 and 0
(TimRefSel[1:0]) within the Framer Operating Mode Register to "[1, 1]" as depicted below.
Transmit E3 Configuration Register - G.832 (Direct Address = 0x1130)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
TxDL in NR
Reserved
TxAIS
Enable
TxLOS
Enable
Transmit MA
Byte based
upon
Receive
Conditions
R/O
R/W
R/O
R/W
0
1