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XRT79L71
PRELIMINARY
253
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
Operation of the Receive Payload Data Output Interface Block
The Receive Payload Data Output Interface block permits the user to configure it to operate in either of the
following modes.
The Serial Mode
The Nibble-Parallel Mode.
4.3.6.1
Serial Mode Operation of the Receive Payload Data Output Interface
If the Receive Payload Data Output Interface Block is configured to operate in the Serial Mode then further
configuriguration of the Receive Payload Data Output Interface block can be made to operate in either the
"Non-Gapped Clock" Mode or in the "Gapped Clock" Mode.
4.3.6.1.1
Operating the Receive Payload Data Output Interface in the "Non-Gapped Clock" Mode
If the Receive Payload Data Output Interface block is configured to operate in the "Serial/Non-Gapped-Clock"
Mode, then all of the following is true.
The XRT79L71 will output the entire contents of the incoming DS3 data-stream consisting of both payload
and overhead bits via the RxSer output pin, upon the rising edge of the RxCLK signal which is a 44.736MHz
clock signal.
The user will need to rely on the RxOHInd/RxGapClk output pin in order to distinguish a payload bit from an
overhead bit, within the data that is output via the RxSer output pin.
The XRT79L71 will pulse the RxFrame output pin "High" for one RxCLK period, coincident to whenever it
outputs the very first bit within a given DS3 frame via the RxSer output pin. The RxFrame output pin will be
held "Low" at all other times.
Figure 107 presents an illustration of how to interface the System-Side Terminal Equipment to the Receive
Payload Data Output Interface block of the XRT79L71, for Serial Mode Operation.
Whenever the XRT79L71 has been configured to operate in this mode, then the Receive Payload Data Output
Interface block will function as the source of the 44.736MHz clock signal via the RxCLK output signal. This
clock signal is used as the System-Side Terminal Equipment clock source by both the Receive Payload Data
Output Interface block of the XRT79L71 and the System-Side Terminal Equipment device or circuitry.
The Receive Payload Data Output Interface block will serially output the entire contents of the incoming DS3
data-stream via the RxSer output pin. As mentioned earlier, the Receive Payload Data Output Interface block
FIGURE 107. AN ILLUSTRATION OF HOW TO INTERFACE THE SYSTEM-SIDE TERMINAL EQUIPMENT TO THE RECEIVE
PAYLOAD DATA OUTPUT INTERFACE BLOCK OF THE XRT79L71 FOR SERIAL MODE OPERATION
System-Side Terminal Equipment
(Receive Payload Section)
XRT79L71 DS3/E3 Framer
DS3_Data_In
Rx_DS3_Clock_In
Rx_Start_of_Frame
RxClk
RxFrame
RxOHInd
44.736 MHz Clock Signal
RxSer
Rx_DS3_OH_Ind