PRELIMINARY
XRT79L71
534
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
1.
1.These "Performance Monitor" Registers will cease to increment anytime the Receive E3 Framer block is
declaring the "OOF" or "LOF" defect condition.
2.
For instructions on how to read out these "Performance Monitor" Registers, please see Section 1.4.
6.3.2.9
Declaring and Clearing the Payload-Type Mismatch Defect Condition
6.3.2.10
Monitoring the GC Byte within the incoming E3 data-stream
6.3.2.11
Monitoring the NR Byte within the incoming E3 data-stream
6.3.3
RECEIVE TRAIL-TRACE MESSAGE CONTROLLER BLOCK
The Receive Trail-Trace Message Controller block is the third functional block within the Receive Direction of
the XRT79L71 that we will discuss for E3, ITU-T G.832 Clear-Channel Framer Applications.
presents an illustration of the Receive Direction circuitry, whenever the XRT79L71 has been configured to
operate in the E3, ITU-T G.832 Clear-Channel Framer Mode, with the Receive Trail-Trace Message Controller
block highlighted.
6.3.3.1
AN INTRODUCTION TO TRAIL-TRACE MESSAGES
If the XRT79L71 is operating in the E3, ITU-T G.832 Frame Format, then the TR (Trail-Trace) Byte can be used
to receive Trail-Trace Messages, also known as a Trail Access Point Identifier. The purpose of the Trail
Access Point Identifier Message is to permit a given terminal to repetitively identify itself, thereby permitting the
Receiving Terminal to verify its continued connection to the correct terminal, via the E3 Transport Medium.
FIGURE 250. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHEN-
EVER THE
XRT79L71 HAS BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.832 CLEAR-CHANNEL FRAMER
MODE (WITH THE RECEIVE TRAIL-TRACE MESSAGE CONTROLLER BLOCK HIGHLIGHTED)
Receive
Payload Data
Input
Interface
Block
Receive
Payload Data
Input
Interface
Block
Receive
DS3/E3
Framer
Block
Receive
DS3/E3
Framer
Block
Receive
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
RxSer
RxNib[3:0]
RxClk
RRING
RTIP
Receive
Overhead Data
Input Interface
Block
Receive
Overhead Data
Input Interface
Block
RxOHClk
RxOHInd
RxOH
RxOHEnable
RxOHFrame
RxNibClk
RxFrame
Rx LAPD
Controller
Block
Rx LAPD
Controller
Block
From Microprocessor
Interface Block
Rx LAPD
Buffer
(90 Bytes)
Rx LAPD
Buffer
(90 Bytes)
Rx TTM
Controller
Block
Rx TTM
Controller
Block
Rx SSM
Controller
Block
Rx SSM
Controller
Block