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XRT79L71
PRELIMINARY
45
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
During the first (of the two) read operations (to a given PMON Register), the user can read out either the
"MSB" or the "LSB" Register.
However, as the user executes this "first" read operation, the entire 16-bit contents of this particular PMON
register will be cleared to "0x0000". The XRT79L71 will store the contents of the "un-read" register into the
"PMON Holding Register (Address = 0x116C).
Therefore, during the second (of the two) read operations (to a given PMON Register), the user MUST obtain
the contents of the "un-read" byte, from the PMON Holding Register.
This method for reading out the PMON Registers, applies to the following PMON Registers.
a.
PMON Excessive Zero Count Registers
b. PMON Line Code Violation Count Registers
c.
PMON Framing Bit/Byte Error Count Registers
d. PMON Parity/P-Bit Count Registers
e.
PMON FEBE Event Count Registers
f.
PMON CP-Bit Error Count Registers
g. PRBS Error Count Registers
3.0
INTERRUPT STRUCTURE WITHIN THE XRT79L71
The XRT79L71 is equipped with a sophisticated Interrupt Servicing Structure. This Interrupt Structure includes
an Interrupt Request output pin (INT), numerous Interrupt Enable Registers and numerous Interrupt Status
Registers. The Interrupt Servicing Structure, within the XRT79L71 IC contains two levels of hierarchy. The top
level is at the Functional Block level (e.g., the Receive ATM Cell Processor Block, the Receive PPP Packet
Processor Block, the Receive DS3/E3 Framer block, etc). The lower hierarchical level is at the individual or
source level. Each hierarchical level consists of a complete set of Interrupt Status Registers/bits and Interrupt
Enable Registers/bits, as will be discussed below.
Most of the functional blocks within the XRT79L71 are capable of generating Interrupt Requests to the C/P.
The XRT79L71 Interrupt Structure has been carefully designed to allow the user to quickly determine the exact
source of the interrupt (with a minimum number of read operations, and, in-turn, minimal latency) which will aid
the C/P in determine the appropriate interrupt service routine to call up in order to either eliminate, or
properly respond to the condition(s) causing the interrupt.
Table 7 lists all of the possible conditions that can generate interrupts, within each functional block of the
XRT79L71.