
XRT79L71
PRELIMINARY
29
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
WR/R/W
B16
I
Write Strobe/Read-Write Operation Identifier:
The function of this input pin depends upon which mode the Microprocessor
Interface has been configured to operate in.
Intel-Asynchronous Mode - WR - Write Strobe Input:
If the Microprocessor Interface is configured to operate in the Intel-Asynchro-
nous Mode, then this input pin functions as the WR (Active Low WRITE Strobe)
input signal from the Microprocessor. Once this active-low signal is asserted,
then the input buffers (associated with the Bi-Directional Data Bus pin, D[7:0])
will be enabled. The Microprocessor Interface will latch the contents on the Bi-
Directional Data Bus (into the "target" register or address location, within the
XRT79L71) upon the rising edge of this input pin.
Motorola-Asynchronous Mode - R/W - Read/Write Operation Identification
Input Pin:
If the Microprocessor Interface is operating in the "Motorola-Asynchronous
Mode", then this pin is functionally equivalent to the "R/W" input pin. In the
Motorola Mode, a "READ" operation occurs if this pin is held at a logic "1", coin-
cident to a falling edge of the
RD/DS (Data Strobe) input pin. Similarly a WRITE
operation occurs if this pin is at a logic "0", coincident to a falling edge of the
RD/DS (Data Strobe) input pin.
Power PC 403 Mode - R/W - Read/Write Operation Identification Input:
If the Microprocessor Interface is configured to operate in the Power PC 403
Mode, then this input pin will function as the "Read/Write Operation Identification
Input" pin.
Anytime the Microprocessor Interface samples this input signal at a logic low
(while also sampling the CS input pin "low") upon the rising edge of
PCLK, then
the Microprocessor Interface will (upon the very same rising edge of
PCLK)
latch the contents of the Address Bus (A[14:0]) into the Microprocessor Interface
circuitry, in preparation for this forthcoming READ operation. At some point
(later in this READ operation) the Microprocessor will also assert the DBEN/
OE
input pin, and the Microprocessor Interface will then place the contents of the
"target" register (or address location within the XRT79L71) upon the Bi-Direc-
tional Data Bus pins (D[7:0]), where it can be read by the Microprocessor
Anytime the Microprocessor Interface samples this input signal at a logic high
(while also sampling the CS input pin a logic "low") upon the rising edge of
PCLK, then the Microprocessor Interface will (upon the very same rising edge
of
PCLK) latch the contents of the Address Bus (A[14:0]) into the Microproces-
sor Interface circuitry, in preparation for the forthcoming WRITE operation. At
some point (later in this WRITE operation) the Microprocessor will also assert
the RD/DS/WE input pin, and the Microprocessor Interface will then latch the
contents of the Bi-Directional Data Bus (D[7:0]) into the contents of the "target"
register or buffer location (within the XRT79L71).
Table 3: List and Brief Description of the Microprocessor Interface Pins
PIN NAME
PIN/BALL
NUMBER
TYPE
DESCRIPTION