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XRT79L71
PRELIMINARY
505
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
6.2.6.4
TRANSMITTING THE FEBE/REI (FAR-END BLOCK ERROR/REMOTE ERROR) INDICATOR
If the Transmit DS3/E3 Framer block is configured to support the E3, ITU-T G.832 framing format, then it will be
capable of transmitting the FEBE/REI indicator to the remote terminal equipment.
The purpose of the FEBE/REI bit-field, within the MA byte of an E3 frame, is two-fold.
1.
It permits a Terminal which is transmitting an E3 data-stream to the remote terminal to determine whether
or not this remote terminal is receiving its E3 data, in an error-free manner.
2.
It permits a Terminal which is receiving an E3 data-stream from a remote terminal to inform this remote
terminal when it is receiving erred E3 frames.
The role of the FEBE/REI bit-field within the MA byte is best presented in the practical example below.
Example:
Consider a Near-End terminal that is communicating with a remote terminal. This Near-End terminal consists
of the Transmit DS3/E3 Framer block and the Receive DS3/E3 Framer block within the XRT79L71, as depicted
The Transmit DS3/E3 Framer block will generate and transmit E3 frames to the remote terminal. Likewise, the
Receive DS3/E3 Framer block will receive and process E3 frames, originating from the remote terminal. The
Near-End Receive DS3/E3 Framer block (e.g., the Receive DS3/E3 Framer block within this particular device)
is going to verify the values of the EM (Error Monitor) byte within the incoming E3 frames from the remote
terminal equipment. If the Near-End Receive DS3/E3 Framer block detects no EM byte errors in the incoming
E3 frame, then it will notify the remote terminal of this fact by forcing the Near-End Transmit DS3/E3 Framer
FIGURE 236. ILLUSTRATION OF THE NEAR-END TRANSMIT DS3/E3 FRAMER BLOCK TRANSMITTING AN E3 FRAME TO
THE REMOTE TERMINAL EQUIPMENT WITH THE
FERF/RDI BIT-FIELD SET TO "0"
Transmit Payload
Data Input
Interface Block
Transmit DS3/E3
Framer Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
DS3/E3
Jitter
Attenuator
Block
Receive DS3/E3
Framer Block
Receive Payload
Data Output
Interface Block
Microprocessor
Interface
TxSer
TxNib[3:0]
TxInClk
MOTO
D[7:0]
A[8:0]
IntB*
CSB*
RdB_DS
WrB_RW
Rdy_Dtck
Reset*
ALE_AS
RxSer
RxNib[3:0]
RxOutClk
Tx LAPD Buffer/
Controller
Rx LAPD Buffer/
Controller
Transmit Overhead
Input
Interface Block
Receive Overhead
Output
Interface Block
TxOHClk
TxOHIns
TxOHInd
TxOH
TxOHEnable
TxOHFrame
TxNibClk
TxFrame
RxNibClk
RxFrame
RxOHFrame
RxOH
RxOHClk
RxOHEnable
RxOHInd
Transmit
DS3/E3
LIU Block
Transmit
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
Receive
DS3/E3
LIU Block
TTIP
TRING
RTIP
RRING
Only one JA exists.
Can be configured in
Tx or Rx Path
No Defects Declared
0
Next Outbound
E3 Frame
FERF/RDI bit (within MA byte) is set to
“0” to denote Normal Condition