
XRT79L71
PRELIMINARY
519
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
The Receive E3 Framer block's operation, while in the OOF State is a unique mix of the Framing Maintenance
and Frame Acquisition operations. In the OOF State the Receive E3 Framer block will exhibit some Frame
Acquisition operational characteristics by attempting to locate the FA1 and FA2 bytes. However, the Receive
E3 Framer block will also exhibit some Frame Maintenance operational behavior by still using the most recent
frame synchronization for its overhead and payload byte processing.
What happens when the Receive E3 Framer block transitions into the OOF State?
As the Receive E3 Framer block transitions from the In-Frame into the OOF State, it will inform the
Microprocessor of this fact by doing all of the following.
Declaring the OOF Defect Condition
The Receive E3 Framer block will indicate that it is declaring the OOF Defect Condition by setting bit 5 (OOF
Defect Declared), within the Receive E3 Configuration and Status Register # 2, to "1" as depicted below.
Generating the Change in OOF Defect Condition Interrupt
FIGURE 248. THE STATE MACHINE DIAGRAM FOR THE RECEIVE E3 FRAMER BLOCK'S FRAME ACQUISITION/MAIN-
TENANCE
ALGORITHM (WITH THE OOF STATE SHADED)
Receive E3 Configuration and Status Register # 2 - G.832 (Direct Address = 0x1111)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive LOF
Algo
LOF Defect
Declared
OOF Defect
Declared
LOS Defect
Declared
AIS Defect
Declared
RxPLD
Unstab
RxTMark
FERF Defect
Declared
R/W
R/O
0
1
0
FA1, FA2
Octet
Search
FA1, FA2
Octet
Search
LOF
State
LOF
State
OOF
State
OOF
State
In Frame
State
In Frame
State
FA1, FA2
Octet
Verification
FA1, FA2
Octet
Verification
FA1 and FA2 Octets
are detected Once
FA1 and FA2 Octets are
NOT Detected
FA1 and FA2 Octets
Are verified once
4 Consecutive
Invalid Frames
3 Consecutive
Valid Frames
1 or 3ms of operating
In the “OOF State”
(User Selectable)
Frame Maintenance
Mode