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XRT79L71
PRELIMINARY
411
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
NOTE: The asterisk (*) indicates that these particular overhead bits will only be processed if BIP-4 processing is enabled,
within the Receive E3 Framer block.
Figure 187 presents an illustration of the behavior of the "RxOH", "RxOHFrame", "RxOHEnable" and "RxClk"
output signals, whenever "Method 2" is used.
5.3.5
THE RECEIVE PAYLOAD DATA OUTPUT INTERFACE BLOCK
The Receive Payload Data Output Interface block is the seventh (and final) functional block (within the Receive
Direction) of the XRT79L71 that we will discuss for E3, ITU-T G.751 Clear-Channel Framer Applications.
Figure 188 presents an illustration of the "Receie Direction" circuitry whenever the XRT79L71 has been
configured to operate in the E3, ITU-T G.751 Clear-Channel Framer Mode, with the "Receive Payload Data
Output Interface" block highlighted.
TABLE 50: THE RELATIONSHIP BETWEEN THE NUMBER OF PULSES IN THE "RXOHENABLE" SIGNAL, SINCE THE
RXOHFRAME SIGNAL WAS LAST SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS BEING OUTPUT (VIA THE RXOH
OUTPUT PIN
) BY THE RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
NUMBER OF PULSES IN RXOHENABLE SINCE RXOHFRAME
BEING SAMPLED
"HIGH
"THE OVERHEAD BIT TO BE OUTPUT BY THE RECEIVE
OVERHEAD DATA OUTPUT INTERFACE BLOCK
0 (RxOHEnable and RxOHFrame are sampled "high" simul-
taneously)
FAS, BIT 1 (MSB)
1
FAS, BIT 2
2
FAS, BIT 3
3
FAS, BIT 4
4
FAS, BIT 5
5
FAS, BIT 6
6
FAS, BIT 7
7
FAS, BIT 8
8
FAS, BIT 9
9
FA2, BIT 10 (LSB)
10
A BIT
11
N BIT
12
BIP-4, BIT 1 (MSB)*
13
BIP-4, BIT 2*
14
BIP-4, BIT 3*
15
BIP-4, BIT 4 (LSB)*
Figure 187. An illustration of the behavior of Receive Overhead Data Output Interface block signals,
whenever the "Method 2" approach to Data Extraction is used