![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT79L71IB-F_datasheet_100145/XRT79L71IB-F_577.png)
PRELIMINARY
XRT79L71
562
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NOTE: About
The answer to the Is k = Msg_Size? Decision Diamond in the flow-chart was obtained during STEP 10 (see
above).
6.3.5.3
Receive LAPD Controller Block Interrupt
6.3.6
RECEIVE OVERHEAD DATA OUTPUT INTERFACE BLOCK
The Receive Overhead Data Output Interface block is the sixth functional block (within the Receive Direction)
of the XRT79L71 that we will discuss for E3, ITU-T G.832 Clear-Channel Framer Applications. Figure 258 presents an illustration of the "Receive Direction" circuitry, whenever the XRT79L71 has been configured to
operate in the E3, ITU-T G.832 Clear-Channel Framer Mode, with the Receive Overhead Data Output Interface
block highlighted.
FIGURE 257. FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE TO READING OUT THE CONTENTS OF THE
NEWLY RECEIVE
LAPD/PMDL MESSAGE FROM THE RECEIVE LAPD MESSAGE BUFFER
START
Set Init_Addr = 0x80
Set k = 1
Set Init_Addr = 0x80
Set k = 1
Write “Init_Addr” into Address Location 0x11C0
Write “Payload_Byte[k]” into Address Location 0x11C1
Is
k == Msg_Size?
Is
k == Msg_Size?
k += 1
END
YES
NO
Init_Addr += 1