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PRELIMINARY
XRT79L71
384
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
The Receive E3 Framer block will also generate the "Change in AIS Defect Condition" Interrupt request by
asserting the Interrupt Output pin (e.g., by pulling it "LOW"), and setting Bit 0 (Change in AIS Defect
Condition Interrupt Status), within the "Receive E3 Interrupt Status Register # 1" to "1" as depicted below.
5.3.2.5
DECLARING AND CLEARING THE FERF/RDI DEFECT CONDITION
If the Receive DS3/E3 Framer block has NOT been configured to compute and verify the BIP-4 Nibble value
(within the incoming E3 data-stream), then it will have the responsibility for declaring and clearing the "FERF/
RDI" defect condition.
Tto have the Receive E3 Framer block declare and clear the FERF/RDI defect conditions, the user MUST
configure the Receive E3 Framer block to NOT compute and verify the BIP-4 Nibble value (within the incoming
E3 data-stream).
Implement this configuration, by setting Bit 0 (RxBIP-4 Enable), within the Receive E3
Configuration and Status Register # 1" to "0" as depicted below.
5.3.2.5.1
Declaring the FERF/RDI (Far-End Receiv Failure/Remote Defect Indicator) Defect Condition
If the Receive E3 Framer block has NOT been configured to compute and verify the BIP-4 Nibble value (within
the incoming E3 data-stream), then it will declares the FERF or RDI defectr condition, if it starts to receive E3
frames in which the "A" bit-field is set to "1".
NOTE: If the Receive E3 Framer block has been configured to compute and verify the BIP-4 nibble (within the incoming E3
data-stream) then it will interpret the "A" bit-field being set to "1" as a FEBE/REI indicator.
Please see
Receive E3 Configuration and Status Register # 2 - G.751 (Address = 0x1111)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
LOF
Algo
LOF
Defect
Condition
Declared
OOF
Defect
Condition
Declared
LOS
Defect
Condition
Declared
AIS Defect
Condition
Declared
Unused
FERF/RDI
Defect
Condition
Declared
R/W
R/O
X
0
Receive E3 Interrupt Status Register # 1 - G.751 (Address = 0x1114)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
COFA
Interrupt
Status
Change in
OOF Defect
Condition
Interrupt
Status
Change in
LOF Defect
Condition
Interrupt
Status
Change in
LOS Defect
Condition
Interrupt
Status
Change in
AIS Defect
Condition
Interrupt
Status
R/O
RUR
0
1
Receive E3 Configuration and Status Register # 1 - G.751 (Address = 0x1110)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
RxFERF
Algo
Unused
RxBIP-4
Enable
R/O
R/W
R/O
R/W
0
X
0