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XRT79L71
PRELIMINARY
575
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
RxOHInd/
RxGapClk
C6
O
Receive Overhead Bit Indicator Output/Receive Gap-Clock Output:
The function of this output pin depends upon whether the XRT79L71 has
been configured to operate in the Non-Gapped Clock or the Gapped-
Clock Mode.
Non-Gapped Clock Mode - RxOHInd:
This output pin will pulse "high", for one "RxClk" period, coincident to
whenever the Receive Payload Data Output Interface block outputs an
overhead bit via the "RxSer" output pin. This output pin will be held "low"
at all other times. The purpose of this output pin is to alert the System-
Side Terminal Equipment that the current bit (e.g., the one that is cur-
rently residing on the RxSer output pin) is an overhead bit and should
not be processed by the System-Side Terminal Equipment.
The XRT79L71 will update this output signal upon the rising edge of
RxClk. Therefore, design (or configure) the System-Side Terminal
Equipment to sample this signal (along with the data on the RxSer out-
put pin) on the falling edge of the RxClk signal.
NOTE: For E3 Applications, this output pin is active in the "RxOHInd"
role, if the Receive Payload Data Output Interface block has
been configured to operate in either the Serial or the Nibble-
Parallel Mode. This output pin will be held "low" at all times.
This is in contrast to DS3 applications, in which is pin is only
active for "Serial" Mode operation.
Gapped Clock Mode - RxGapClk:
In this mode this output pin will function as a "payload bit" output clock
signal. In other words, the Receive Payload Output Interface block will
only generate a clock pulse (via this output pin) coincident to when it out-
puts a payload bit via the RxSer output pin. The Receive Payload Data
Output Interface block will NOT generate a clock edge (via this output
pin) coincident to whenever it outputs an overhead bit via the "RxSer"
output pin. As a consequence, there will be "gaps" within this particular
clock output signal (hence the name "Gapped Clock Mode").
If the XRT79L71 is configured to operate in the Gapped Clock Mode,
then design or configure the System-Side Terminal Equipment to sample
and latch the "RxSer" data upon the falling edge of the "RxOHInd/
RxGapClk" clock signal.
RxFrame
B6
O
Receive Payload Data Output Interface - Receive Start of Frame
Output Indicator:
The behavior of this output pin depends upon whether the XRT79L71
has been configured to operate in the "Serial" or in the "Nibble-Parallel"
Mode.
Serial Mode Operation
The Receive Payload Data Output Interface block will pulse this output
pin "high" (for one RxCLK period) coincident to whenever it outputs the
very first bit of a new E3 frame via the "RxSer" output pin. This output
pin will remain "low" at all other times.
Nibble-Parallel Mode Operation
The Receive Payload Data Output Interface block will pulse this output
pin "high" (for one RxCLK or "Nibble-Period") coincident to whenever it
outputs the very first nibble of a new E3 frame via the "RxNib[3:0]" output
pins. This output pin will remain "low" at all other times.
TABLE 73: LIST AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE RECEIVE PAYLOAD DATA OUTPUT
INTERFACE BLOCK
SIGNAL NAME
PIN/BALL
NUMBER
TYPE
DESCRIPTION