
XRT79L71
PRELIMINARY
267
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
The Transmit E3 LIU block
5.2.1
TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK
The Transmit Payload Data Input Interface block is the very first functional block within the Transmit Direction
of the XRT79L71 that we will discuss for E3, ITU-T G.751 Clear-Channel Framer Applications. Figure 123 presents an illustration of the Transmit Direction circuitry whenever the XRT79L71 has been configured to
operate in the E3, Clear-Channel Framer Mode, with the Transmit Payload Data Input Interface block
highlighted.
The purpose of the Transmit Payload Data Input Interface block is to accept payload data from system-side or
up-stream source and to pass this payload data along to the Transmit E3 Framer block that will ultimately map
this payload data into the payload bytes within each outbound E3 frame.
In order to accomplish this, the Transmit Payload Data Input Interface block has numerous input and output
pins. Table 36 presents a list and a brief description of each of these pins.
FIGURE 123. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE TRANSMIT DIRECTION CIRCUITRY, WHEN-
EVER THE
XRT79L71 HAS BEEN CONFIGURED TO OPERATE IN THE E3, ITU-T G.751 CLEAR-CHANNEL FRAMER
MODE (WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK HIGHLIGHTED)
Transmit
Payload Data
Input
Interface
Block
Transmit
Payload Data
Input
Interface
Block
Transmit
DS3/E3
Framer
Block
Transmit
DS3/E3
Framer
Block
Transmit
DS3/E3
LIU Block
Transmit
DS3/E3
LIU Block
TxSer
TxNib[3:0]
TxInClk
TRING
TTIP
Transmit
Overhead Data
Input Interface
Block
Transmit
Overhead Data
Input Interface
Block
TxOHClk
TxOHIns
TxOHInd
TxOH
TxOHEnable
TxOHFrame
TxNibClk
TxFrame
Tx LAPD
Controller
Block
Tx LAPD
Controller
Block
From Microprocessor
Interface Block
Tx LAPD
Buffer
(90 Bytes)
Tx LAPD
Buffer
(90 Bytes)
Tx TTM
Controller
Block
Tx TTM
Controller
Block
Tx SSM
Controller
Block
Tx SSM
Controller
Block