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XRT79L71
PRELIMINARY
297
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
sampled "High". By doing this, the System-Side Terminal Equipment will be able to keep track of which
overhead bit is currently being processed by the Transmit Overhead Data Input Interface block at any given
TxOHClk clock period.
When the System-Side Terminal Equipment knows which overhead bit is being
processed within a given TxOHClk clock period, it can decide when to insert the appropriate bit-value into the
Transmit Overhead Data Input Interface block (and in-turn, force the Transmit DS3/E3 Framer block to insert
this same bit-value into the appropriate overhead bit-position within the outbound E3 data-stream). From all of
this, the System-Side Terminal Equipment will know when it should assert the TxOHIns input pin and place the
appropriate value on the TxOH input pin of the XRT79L71.
Table 40 relates the number of rising clock edge, within the TxOHClk output signal, since the TxOHFrame
output signal was sampled "High" to the E3 Overhead Bit being processed by the Transmit Overhead Data
Input Interface block. The user can use this table as a guide for inserting the appropriate overhead bits, within
the outbound E3 data-stream, for Method 1.
NOTES:
1.
The shaded rows designate those Overhead bits that the XRT79L71 can be used to insert into the outbound E3
data-stream via the Transmit Overhead Data Input Interface block.
The un-shaded rows designate those
Overhead bits that the XRT79L71 CANNOT insert into the outbound E3 data-stream.
2.
The asterisk (*) indicates that these particular overhead bits will only be processed if BIP-4 processing is enabled,
within the Transmit E3 Framer Block.
TABLE 40: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN THE TXOHCLK SIGNAL, SINCE
THE
TXOHFRAME SIGNAL WAS LAST SAMPLED "HIGH" TO THE E3 OVERHEAD BIT THAT IS BEING PROCESSED BY THE
TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK
NUMBER OF RISING EDGES IN TXOHCLK
SINCE
TXOHFRAME BEING SAMPLED
"HIGH"
THE OVERHEAD BIT TO BE PROCESSED
BY THE
TRANSMIT OVERHEAD DATA
INPUT INTERFACE BLOCK
CAN THIS OVERHEAD BIT BE ACCEPTED
BY THE
XRT79L71, AND INSERTED INTO
THE OUTBOUND
E3 DATA-STREAM?
0 (TxOHClk, Clock Edge is coincident
with the TxOHFrame signal being sam-
pled "High")
FAS, Bit 1 (MSB)
NO
1
FAS, Bit 2
NO
2
FAS, Bit 3
NO
3
FAS, Bit 4
NO
4
FAS, Bit 5
NO
5
FAS, Bit 6
NO
6
FAS, Bit 7
NO
7
FAS, Bit 8
NO
8
FAS, Bit 9
NO
9
FAS, Bit 10 (LSB)
NO
10
A Bit
YES
11
N Bit
YES
12
BIP-4, Bit 1 (MSB)*
NO
13
BIP-4, Bit 2*
NO
14
BIP-4, Bit 3*
NO
15
BIP-4, Bit 4*
NO