PRELIMINARY
XRT79L71
298
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
TASK # 3: After the System-Side Terminal Equipment has waited the appropriate number of clock edges from
the TxOHFrame signal being sampled "High", it should assert the TxOHIns input signal (by pulling it "High").
Concurrently, the System-Side Terminal Equipment should also place the appropriate value of the overhead bit
(to be inserted into the outbound E3 data-stream) onto the TxOH input signal. The Transmit Overhead Data
Input Interface block will sample and latch the data (residing on the TxOH input pin) upon the very next falling
edge of the TxOHClk output signal.
TASK # 4: The System-Side Terminal Equipment should hold the TxOHIns input pin "High" and also hold the
value of the TxOH signal stable until the next rising edge of TxOHClk is detected. Afterwards, the System-Side
Terminal Equipment should toggle the TxOHIns input pin "Low" and wait until another appropriate TxOHClk
period come up, for inserting an overhead bit into the outbound E3 data-stream.
CASE STUDY: The System-Side Terminal Equipment intends to insert the appropriate overhead bits
into the Transmit Overhead Data Input Interface using Method 1 in order to transmit the FERF/RDI
indicator to the remote terminal equipment.
For E3, ITU-T G.751 applications, the FERF/RDI indication is transmitted by setting the "A" bit-field (of each
outbound E3 frame) to "1".
If we were to assume that the connection between the System-Side Terminal Equipment and the Transmit
Overhead Data Input Interface block (of the XRT79L71) is as illustrated in Figure 139, then Figure 140 presents an illustration of the signaling that must go on between the System-Side Terminal Equipment and the
Transmit Overhead Data Input Interface, when using Method 1.
In Figure 140, the System-Side Terminal Equipment samples the TxOHFrame signal being "High" during
Rising Edge Clock Edge # 0 with the TxOHClk signal. At this point, the System-Side Terminal Equipment
knows that the XRT79L71 is just about to process the very first overhead bit within a given E3 frame.
According to Table 40, the "A" bit will be processed at TxOHClk clock edge # 10. In order to facilitate the
transmission of the FERF/RDI indicator, the System-Side Terminal Equipment must (1) wait for 10 TxOHClk
clock periods, and (2) then set this particular bit-field to "1". Once the System-Side Terminal Equipment has
FIGURE 140. ILLUSTRATION OF THE SIGNALING THAT MUST OCCUR BETWEEN THE SYSTEM-SIDE TERMINAL EQUIP-
MENT AND THE
TRANSMIT OVERHEAD DATA INPUT INTERFACE OF THE XRT79L71, IN ORDER TO CONFIGURE THE
XRT79L71 TO TRANSMIT THE FERF/RDI INDICATOR TO THE REMOTE TERMINAL EQUIPMENT (USING METHOD 1)
System-Side Terminal Equipment/XRT79L71 Transmit Overhead Data Input Interface Signals
TxOHClk
TxOHIns
TxOHFrame
TxOH
Remaining Overhead Bits within the E3 Frame
A = 1
TxOHFrame is sample “high”
System-Side Terminal Equipment
Asserts “TxOHIns” and data on
“TxOH” line.
XRT79L71 device samples the “TxOHIns and
TxOH input signals upon falling of TxOHClk
After 10 rising edges of TxOHClk, the
System-Side Terminal Equipment asserts
The “TxOHIns” and places data on the
“TxOH” line”
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