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PRELIMINARY
XRT79L71
544
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NOTE: Since this particular interrupt is the "Change in SSM" Interrupt, then Bit 2 (DS3/E3 Framer Block Interrupt Status)
within the "Operation Interrupt Status Register - Byte 1" Register will be set to "1" as indicated above.
STEP 2 - Determine whether this particular interrupt occurred within the Transmit or Receive DS3/E3
Framer block.
This can be accomplished by reading out the contents of the "Framer Block Interrupt Status" Register. Since
we are discussing the "Change in SSM Message" Interrupt, then Bit 7 (Receive DS3/E3 Framer Block Interrupt
Status) should be set to "1" as depicted below.
STEP 3 - Determine which Receive DS3/E3 Framer block interrupt has been requested.
This is accomplished by reading out the contents of both the "Receive E3 Interrupt Status Register # 1 and # 2"
as depicted below.
Operation Interrupt Status Register - Byte 0 (Address = 0x0113)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
UTOPIA/
POS-PHY
Interface
Block
Interrupt
Status
Unused
Receive ATM
Cell/PPP
Processor
Block Inter-
rupt Status
Transmit
UTOPIA/
POS-PHY
Interface
Block
Status
Unused
Transmit
ATM
Cell/PPP
Processor
Block
Interrupt
Status
R/O
0
Framer Block Interrupt Status Register (Address = 0x1105)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Receive
DS3/E3
Framer
Block
Interrupt
Status
Receive
PLCP
Processor
Block
nterrupt
Status
Unused
Transmit
DS3/E3
Framer
Block
Interrupt
Status
One
Second
Interrupt
R/O
RUR
1
0
Receive E3 Interrupt Status Register # 1 - G.832 (Address = 0x1114)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change in
SSM MSGI
nterrupt
Status
SSM OOS
Interrupt
Status
COFA
Interrupt
Status
Change in
OOF State
Interrupt
Status
Change in
LOF State
Interrupt
Status
Change in
LOS State
Interrupt
Status
Change in
AIS State
Interrupt
Status
R/O
RUR
0
1
0