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PRELIMINARY
XRT79L71
196
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NOTE: The state of Bit 1 (Receive LOS Defect Declared - Receive DS3/E3 LIU Block) within the LIU Alarm Status Register
(at this point) will depend upon the state of Bit 4 (Analog LOS Defect Declared).
It MAY generate the Change of LOS Condition Interrupt.
NOTES:
1.
The XRT79L71 will indicate that it is generating this interrupt by (1) asserting the Interrupt Request output pin, and
(2) by setting Bit 1 (Change of LOS Condition Interrupt), within the LIU Interrupt Status Register to "1" as depicted
below.
2.
The XRT79L71 will only generate this Change of LOS Condition Interrupt if the Digital LOS Detector is also NOT
currently declaring the LOS defect condition.
4.3.1.7
Jitter Attenuator Block
Please see
Section 4.2.6.2 for a description of the Jitter Attenuator Block
4.3.1.8
The B3ZS Decoder Block
The purpose of the B3ZS Decoder block is to decode the inbound DS3 traffic from the B3ZS Line Code, into a
digital data-stream. In the case of the XRT79L71, the B3ZS Decoder block will always be enabled and the
user has no ability to disable the B3ZS Decoder block.
4.3.1.9
Performance Characteristics of the Receive DS3 LIU Block
These next few sections will present the performance characteristics of the Receive DS3/E3 LIU Block, within
the XRT79L71. In particular these sections will address the following parameters for DS3 Applications.
Receive Sensitivity
Interference Margin
Jitter Tolerance
4.3.1.9.1
Receive Sensitivity Capability of the Receive DS3 LIU Block
For DS3 Applications, the Receive DS3 LIU Block MUST be capable of receiving a DSX-3 signal that has been
attenuated by anywhere from 0 to 450 feet of cable loss, and at least 6dB of flat loss, in a un-erred manner.
Table 25 summarizes the Receive Sensitivity of the Receive DS3/E3 LIU Block, within the XRT79L71.
LIU Interrupt Status Register (Address = 0x1302)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change of
FL
Condition
Interrupt
Status
Change of
LOL
Condition
Interrupt
Status
Change of
LOS
Condition
Interrupt
Status
Change of
DMO
Condition
Interrupt
Status
R/O
RUR
0
1
0