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XRT79L71
PRELIMINARY
289
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
System-Side Terminal Equipment should hold (or NOT advance the very next payload bit) to the TxSer input
pin (of the XRT79L71) until it samples the TxOH_Ind output "Low" once again.
In this particular approach, the user must design in the appropriate State Machine circuitry within the System-
Side Terminal Equipment in order to properly respond to the state of the TxOH_Ind output pin, while providing
the payload data to the Transmit Payload Data Input Interface. While designing such a State Machine into a
CPLD or ASIC design is not very difficult, the user can take advantage of an easier approach by configuring the
Transmit Payload Data Input Interface block to operate in the Gapped-Clock Mode.
If the Transmit Payload Data Input Interface block has been configured to operate in the Gapped-Clock
Mode
If the Transmit Payload Data Input Interface block is configured to operate in the Gapped-Clock Mode, then the
role of the TxOH_Ind output pin will change from being the Overhead Indicator output pin, to now being a
demand-clock output pin. In other words, If the Transmit Payload Data Input Interface block is configured to
operate in the Gapped-Clock Mode, then it (the Transmit Payload Data Input Interface block) will generate a
clock pulse (via the TxOH_Ind output pin) if and only if it is ready to accept and process a payload bit. If the
Transmit Payload Data Input Interface block is about to process an overhead bit, then it will not generate a
clock pulse via the TxOH_Ind output pin. This action will result in the Transmit Payload Data Input Interface
block generating a gapped clock signal via the TxOH_Ind output pin (hence the term Gapped-Clock Mode).
If the Transmit Payload Data Input Interface block is configured to operate in the Gapped-Clock Mode, then the
System-Side Terminal Equipment will be expected to update the data on the TxSer input pin (of the XRT79L71)
upon the rising edge of the TxOH_Ind output signal. The XRT79L71 will sample and latch the TxSer data,
upon the falling edge of the TxOH_Ind output signal. In this case, there is no need to check the state of a
certain output pin, and then gate the placement of the next payload bit (on the TxSer input pin) with the
sampled state of this particular signal. The System-Side Terminal Equipment only needs to respond to the
rising edge of this particular Gapped-Clock signal.
If the XRT79L71 has been configured to operate in the Loop-Timing Mode (e.g., Mode 1), then this Gapped-
Clock signal (from the TxOH_Ind output pin) will be derived from the LIU Recovered Clock signal (from the
Receive DS3 LIU Block). Similarly, if the XRT79L71 has been configured to operate in the Local-Timing Mode,
then this Gapped-Clock signal will be derived form the TxInClk input signal.
Configuring the Transmit Payload Data Input Interface block to operate in the Gapped-Clock Mode
To configure the Transmit Payload Data Input Interface block to operate in the Gapped-Clock Mode, do all of
the following.
STEP 1 - the user should interface the System-Side Terminal Equipment to the Transmit Payload Data
Input Interface block, in a manner as indicated below in Figure 136.