![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT79L71IB-F_datasheet_100145/XRT79L71IB-F_333.png)
PRELIMINARY
XRT79L71
318
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
NOTE: About
Figure 146: The value Msg_Size (within the decesion diamond) is the value that the user writes into the
Transmit LAPD Byte Count Register, during STEP 6.
STEP 8 - Enable the Transmit LAPD Interrupt (Optional).
This step is optional. However, if this step is executed, then the XRT79L71 will generate an interrupt to the
Microprocessor, anytime the Transmit LAPD Controller has completed its transmission of a given PMDL
Message.
The procedure for enabling the Transmit LAPD Interrupt is actually a three-step process.
STEP 8a - Enable the DS3/E3 Framer block interrupts - At the Operational Block Level.
This step is accomplished by setting Bit 2 (DS3/E3 Framer Block Interrupt Enable) to "1" as illustrated below.
FIGURE 146. FLOW-CHART DEPICTING AN APPROACH THAT ONE CAN USE TO WRITING IN THE REMAINING BYTES OF
THE
OUTBOUND MESSAGE INTO THE TRANSMIT LAPD MESSAGE BUFFER
START
Set Init_Addr = 0x01
Set k = 1
Set Init_Addr = 0x01
Set k = 1
Write “Init_Addr” into Address Location 0x11C0
Write “Payload_Byte[k]” into Address Location 0x11C1
Is
k == Msg_Size?
Is
k == Msg_Size?
k += 1
END
YES
NO
Init_Addr += 1