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XRT79L71
PRELIMINARY
221
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
NOTE: For instructions on how to read out these "Performance Monitor" Registers please see Section 2.5 It will also increment the One Second - CP-bit/Parity Error Count - Accumulator Register once for each DS3
frame that is determined to have a CP-bit error. The "One Second - CP-Bit/Parity Error Count -Accumulator
Register is located at Address 0x1172 and 0x1173.
NOTE: The Near-End Transmit DS3/E3 Framer block, within this particular XRT79L71, will automatically be configured to
set the three FEBE bit-fields to some value other than [1, 1, 1] in order to indicate an erred condition for each time
in which the Receive DS3 Framer block receives a DS3 frame with erred CP-bits. Please see
Section 4.2.5.6 for
more information on this transmission of the FEBE indicator.
4.3.2.9
DETECTING CHANGES IN THE AIC BIT
As mentioned earlier in this Data Sheet, the AIC (Application Identification Channel) Bit resides within the third
C-bit, within F-Frame # 1 (as depicted in Figure 14). The purpose of the AIC bit within the DS3 data-stream is
to permit a given Terminal Equipment to determine, though not conclusively, if it receiving a DS3 signal is of the
M13/M23 framing format or is of the C-bit Parity framing format.
For C-bit Parity Applications, a given Transmitting DS3 Terminal Equipment will set the AIC bit-field to "1".
However, for Channelized M13/M23 applications, the AIC bit-position within a given DS3 frame is simply a C-
bit that is either set to "0" or "1" in order to denote stuff opportunities that either were or were not taken
whenever this particular DS3 signal was created by multiplexing the seven (7) lower tributary DS2 signals.
PMON CP-Bit Error Count Register - MSB (Address = 0x1158)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_CP-Bit_Error_Count_Upper_Byte[7:0]
RUR
0
PMON CP-Bit Error Count Register - LSB (Address = 0x1159)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_CP-Bit_Error_Count_Lower_Byte[7:0]
RUR
0
One Second - CP Bit Error Accumulator Register - MSB (Address = 0x1172)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
One_Second_CP_Bit_Error_Accum_MSB[7:0]
R/O
0
One Second - CP Bit Error Accumulator Register - LSB (Address = 0x1173)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
One_Second_CP_Bit_Error_Accum_LSB[7:0]
R/O
0