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XRT79L71
PRELIMINARY
223
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
4.3.2.10
DETECTING FEBE (FAR-END BLOCK ERROR) EVENTS
The Receive DS3/E3 Framer block has the responsibility for detecting and tallying the number of times that it
receives disturbed FEBE (Far-End-Block Error) indicators from the remote terminal equipment as described
below.
Each DS3 frame consists of three FEBE bit-fields. The remote terminal equipment which is generating the
incoming DS3 data-stream will set the FEBE bit-fields to values that indicate whether or not the remote
terminal is experiencing any F, M or CP-bit errors. If the remote terminal is currently not experiencing any
errors, then it will set the all of the FEBE bit-fields, within each outbound DS3 data stream to "1". Hence, the
FEBE value for an un-erred condition is "1, 1, 1".
Conversely, if the remote terminal is detecting an F, M or CP-bit errors, then it will proceed to set the FEBE bit-
fields within each outbound DS3 data stream to some value other than "1, 1, 1". The important thing to note is
that the FEBE value is a reflection of the receive condition of the remote terminal equipment, not the local
terminal equipment.
NOTES:
1.
The remote terminal equipment will set the FEBE bit-fields to some value other than [1, 1, 1], within a given
outbound DS3 frame, each time the Near-End Corresponding Receive DS3 Framer block has received a DS3
frame with either a CP-bit or Framing bit error.
2.
The FEBE values within the incoming DS3 data-stream is a reflection of the receive conditions of the remote
terminal equipment, not the local terminal equipment.
If the Receive DS3 Framer block receives any DS3 frames that contain FEBE bits, with values other than "1, 1,
1", then it will increment the PMON FEBE Event Count Register.
The Receive DS3 Framer block will
increment this register once, for each DS3 frame that it receives, in which the FEBE values are not set to "1, 1,
1". The bit-format and address locations of these registers are presented below.
Receive DS3 Interrupt Status Register (Address = 0x1113)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT
BIT 1
BIT 0
Detection of
CP Bit Error
Interrupt
Status
Change of
LOS Defect
Condition
Interrupt
Status
Change of
AIS Defect
Condition
Interrupt
Status
Change of
Idle
Condition
Interrupt
Status
Change of
FERF Defect
Condition
Interrupt
Status
Change of
AIC State
Interrupt
Status
Change of
OOF Defect
Condition
Interrupt
Status
Detection of
P-Bit Error
Interrupt
Status
RUR
0
1
0
PMON FEBE Event Count Register - MSB (Address = 0x1156)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_FEBE_Event_Count_Upper_Byte[7:0]
RUR
0