
PRELIMINARY
XRT79L71
532
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
Each E3 frame consists of a single FEBE/REI bit-field. The remote terminal equipment which is generating the
incoming E3 data-stream will set the FEBE/REI bit-field to the appropriate value that indicates whether or not
the remote terminal is experiencing any EM byte errors. If the remote terminal equipment is currently not
detecting any EM byte errors, then it will set the FEBE/REI bit-field within the MA byte of each outbound E3
frame to "0". Hence, the FEBE/REI value for an un-erred condition is "0".
Conversely, if the remote terminal equipment is detecting EM byte errors, then it will proceed to set the FEBE/
REI bit-field within the MA byte of the very next outbound E3 frame to "1".
NOTES:
1.
The remote terminal equipment will set the FEBE/REI bit-field to "1", within a given outbound E3 frame, each time
the Near-End Corresponding Receive E3 Framer block has received an E3 frame with an erred EM byte.
2.
The FEBE/REI value within the incoming E3 data-stream is a reflection of the receive conditions of the remote
terminal equipment, not the local terminal equipment.
If the Receive E3 Framer block receives any E3 frames, in which the FEBE/REI bit-field is set to "1", then it will
do the following.
It will generate the Detection of FEBE Event Interrupt request, by asserting the Interrupt Output pin (e.g., by
pulling it "Low") and setting Bit 4 (Detection of FEBE Event Interrupt Status), within the Receive E3 Interrupt
Status Register # 2 to "1" as depicted below.
It will increment the PMON FEBE Event Count Register once, for each E3 frame that it receives, in which the
FEBE/REI bit-field was set to "1". The bit-format and address locations of these registers are presented
below.
NOTE: For instructions on how to read out these "Performance Monitor" Registers, please see Section 1.4.
Receive E3 Interrupt Status Register # 2 - G.832 (Address = 0x1115)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
Change in
RxTTB
Message
Interrupt
Status
Reserved
Detection of
FEBE Event
Interrupt
Status
Change in
FERF/RDI
Defect
Condition
Interrupt
Status
Detection of
BIP-8 Error
Interrupt
Status
Detection of
Framing
Byte Error
Interrupt
Status
RxPLD
Mismatch
Interrupt
Status
R/O
RUR
R/O
RUR
0
1
0
PMON FEBE Event Count Register - MSB (Address = 0x1156)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_FEBE_Event_Count_Upper_Byte[7:0]
RUR
0
PMON FEBE Event Count Register - LSB (Address = 0x1157)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
PMON_FEBE_Event_Count_Lower_Byte[7:0]
RUR
0