
PRELIMINARY
XRT79L71
76
REV. P2.0.0
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
4.2.1.2
Mode 2 - Serial/Local-Timing/Frame Slave Mode Operation of the Transmit Payload Data
Input Interface Block
If the XRT79L71 is configured to operate in Mode 2, then all of the following are true.
The XRT79L71 will be configured to operate in the Local-Timing Mode. In other words, the Transmit Section
of the XRT79L71 will use the TxInClk input signal as its timing source.
Since the XRT79L71 is configured to operate in the Serial-Mode, it will sample and latch the data, being
applied to the TxSer input pin upon the rising edge of the TxInClk input signal.
The Transmit Section of the XRT79L71 will initiate the generation and transmission of a new DS3 frame
anytime it detects a rising edge at the TxFrameRef input pin.
The XRT79L71 will still pulse the TxFrame output pin coincident to whenever the Transmit Payload Data
Input Interface block is processing the very last bit within a given DS3 frame.
Figure 32 presents an illustration of the behavior of the System-Side Terminal Equipment to the Transmit
Payload Data Input Interface block of the XRT79L71 for Mode 2 operation.
Mode 2 Operation of the Transmit Payload Data Input Interface Block
Whenever the XRT79L71 has been configured to operate in this mode, then one is required to supply a
44.736MHz clock signal to both the System-Side Terminal Equipment circuitry and the XRT79L71. More
specifically, this 44.736MHz clock signal will be applied to both the DS3_Clock_In input of the System-Side
Terminal Equipment and the TxInClk input pin of the XRT79L71, in parallel.
FIGURE 32. AN ILLUSTRATION OF THE BEHAVIOR OF THE SYSTEM-SIDE TERMINAL EQUIPMENT SIGNALS FOR MODE
2 (SERIAL/LOCAL-TIMING/FRAME-SLAVE) MODE OPERATION
44.736MHz
Clock Source
44.736MHz
Clock Source
System-Side Terminal
Equipment
XRT79L71 DS3/E3
Framer IC
DS3_Data_Out
DS3_Clock_In
Tx_Start_of_Frame
DS3_Overhead_Ind
TxSer
TxInClk
TxFrameRef
TxOH_Ind
NibInt