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參數(shù)資料
| 型號： | SN2005118412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁數(shù)： | 96/271頁 |
| 文件大?。?/td> | 3240K |
| 代理商： | SN2005118412ZHK |
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OHCI Registers
169
September 2005
SCPS110
Table 815. Interrupt Event Register Description (Continued)
BIT
FIELD NAME
TYPE
DESCRIPTION
19
phy
RSCU
Indicates that the PHY layer requests an interrupt through a status transfer.
18
regAccessFail
RSCU
Indicates that a PCIxx12 register access has failed due to a missing SCLK clock signal from the PHY
layer. When a register access fails, bit 18 is set to 1b before the next register access.
17
busReset
RSCU
Indicates that the PHY layer has entered bus reset mode.
16
selfIDcomplete
RSCU
A self-ID packet stream has been received. It is generated at the end of the bus initialization process.
Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.
15
selfIDcomplete2
RSCU
Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1b by the controller when
it sets bit 16 (selfIDcomplete), and retains the state, independent of bit 17 (busReset).
1410
RSVD
R
Reserved. Bits 1410 return 00000b when read.
9
lockRespErr
RSCU
Indicates that the controller sent a lock response for a lock request to a serial bus register, but did
not receive an ack_complete.
8
postedWriteErr
RSCU
Indicates that a host bus error occurred while the controller was trying to write a 1394 write request,
which had already been given an ack_complete, into system memory.
7
isochRx
RU
Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have
generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous
receive interrupt event register at OHCI offset A0h/A4h (see Section 8.25) and isochronous receive
interrupt mask register at OHCI offset A8h/ACh (see Section 8.26). The isochronous receive interrupt
event register indicates which contexts have been interrupted.
6
isochTx
RU
Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts have
generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous
transmit interrupt event register at OHCI offset 90h/94h (see Section 8.23) and isochronous transmit
interrupt mask register at OHCI offset 98h/9Ch (see Section 8.24). The isochronous transmit interrupt
event register indicates which contexts have been interrupted.
5
RSPkt
RSCU
Indicates that a packet was sent to an asynchronous receive response context buffer and the
descriptor xferStatus and resCount fields have been updated.
4
RQPkt
RSCU
Indicates that a packet was sent to an asynchronous receive request context buffer and the descriptor
xferStatus and resCount fields have been updated.
3
ARRS
RSCU
Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1b upon completion of an
ARRS DMA context command descriptor.
2
ARRQ
RSCU
Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1b upon completion of an
ARRQ DMA context command descriptor.
1
respTxComplete
RSCU
Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1b upon completion of
an ATRS DMA command.
0
reqTxComplete
RSCU
Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1b upon completion of an
ATRQ DMA command.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN200512N | 制造商:Texas Instruments 功能描述: |
| SN200513N | 制造商:Texas Instruments 功能描述: |
| SN200515N | 制造商:Texas Instruments 功能描述: |
| SN200520N | 制造商:Texas Instruments 功能描述: |
| SN200530DR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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