
PC Card Controller Programming Model
81
September 2005
SCPS110
4.10 Header Type Register
The header type register returns 82h when read, indicating that the function 0 configuration spaces adhere
to the CardBus bridge PCI header. The CardBus bridge PCI header ranges from PCI registers 00h7Fh, and
80hFFh is user-definable extension registers.
PCI register offset:
0Eh (Function 0)
Register type:
Read-only
Default value:
82h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
1
0
1
0
4.11 BIST Register
Because the controller does not support a built-in self-test (BIST), this register returns the value of 00h when
read.
PCI register offset:
0Fh (Function 0)
Register type:
Read-only
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
4.12 CardBus Socket Registers/ExCA Base Address Register
This register is programmed with a base address referencing the CardBus socket registers and the
memory-mapped ExCA register set. Bits 3112 are read/write, and allow the base address to be located
anywhere in the 32-bit PCI memory address space on a 4-Kbyte boundary. Bits 110 are read-only, returning
000h when read. When software writes FFFF FFFFh to this register, the value read back is FFFF F000h,
indicating that at least 4K bytes of memory address space are required. The CardBus registers start at offset
000h, and the memory-mapped ExCA registers begin at offset 800h.
PCI register offset:
10h
Register type:
Read-only, Read/Write
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
4.13 Capability Pointer Register
The capability pointer register provides a pointer into the PCI configuration header where the PCI power
management register block resides. PCI header doublewords at A0h and A4h provide the power management
(PM) registers. This register is read-only and returns A0h when read.
PCI register offset:
14h
Register type:
Read-only
Default value:
A0h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
1
0
1
0