
OHCI Controller Programming Model
140
September 2005
SCPS110
7.9
TI Extension Base Address Register
The TI extension base address register is programmed with a base address referencing the memory-mapped
TI extension registers. When BIOS writes FFFF FFFFh to this register, the value read back is FFFF C000h,
indicating that at least 16K bytes of memory address space are required for the TI registers. See Table 78
for a complete description of the register contents.
Function 1 register offset: 14h
Register type:
Read/Write, Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 78. TI Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3114
TIREG_PTR
RW
TI register pointer. This field specifies the upper 18 bits of the 32-bit TI base address register. The
default value for this field is all 0s.
134
TI_SZ
R
TI register size. This field returns 0s when read, indicating that the TI registers require a 16K-byte
region of memory.
3
TI_PF
R
TI register prefetch. Bit 3 returns 0b when read, indicating that the TI registers are nonprefetchable.
21
TI_MEMTYPE
R
TI memory type. This field returns 00b when read, indicating that the TI base address register is
32 bits wide and mapping can be done anywhere in the 32-bit memory space.
0
TI_MEM
R
TI memory indicator. Bit 0 returns 0b when read, indicating that the TI registers are mapped into
system memory space.
7.10 CardBus CIS Base Address Register
The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0s when read.
See Table 79 for a complete description of the register contents.
Function 1 register offset: 18h
Register type:
Read/Write, Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 79. CardBus CIS Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3111
CIS_BASE
RW
CIS base address. This field specifies the upper 21 bits of the 32-bit CIS base address. If CARDBUS
is sampled high on a GRST, then this field is read-only, returning 0s when read.
104
CIS_SZ
R
CIS address space size. This field returns 000 0000b when read, indicating that the CIS space
requires a 2K-byte region of memory.
3
CIS_PF
R
CIS prefetch. Bit 3 returns 0b when read, indicating that the CIS is nonprefetchable. Furthermore, the
CIS is a byte-accessible address space, and either a doubleword or 16-bit word access yields
indeterminate results.
21
CIS_MEMTYPE
R
CIS memory type. This field returns 00b when read, indicating that the CardBus CIS base address
register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space.
0
CIS_MEM
R
CIS memory indicator. Bit 0 returns 0b when read, indicating that the CIS is mapped into system
memory space.