
Principles of Operation
55
September 2005
SCPS110
Figure 310 illustrates a byte read. The read protocol is very similar to the write protocol, except the R/W
command bit must be set to 1b to indicate a read-data transfer. In addition, the PCIxx12 master must
acknowledge reception of the read bytes from the slave transmitter. The slave transmitter drives the SDA
signal during read data transfers. The SCL signal remains driven by the PCIxx12 master.
Sb6
b4
b5
b3 b2 b1 b0
0
b7 b6 b5 b4 b3
b2 b1 b0
AA
Slave Address
Word Address
R/W
Sb6
b4
b5
b3 b2 b1 b0
1
A
Slave Address
S/P = Start/Stop Condition
M = Master Acknowledgement
b7 b6
b4
b5
b3 b2 b1 b0
M
P
Data Byte
Start
Restart
R/W
A = Slave Acknowledgement
Stop
Figure 310. Serial-Bus Protocol—Byte Read
Figure 311 illustrates EEPROM interface doubleword data collection protocol.
S1
1
0
b7 b6 b5 b4 b3
b2 b1 b0
AA
Slave Address
Word Address
R/W
Data Byte 2
Data Byte 1
Data Byte 0
M
P
M
M = Master Acknowledgement
S/P = Start/Stop Condition
A = Slave Acknowledgement
Data Byte 3
M
S1
1
0
001
A
Restart
R/W
Slave Address
Start
Figure 311. EEPROM Interface Doubleword Data Collection
3.6.4 Serial-Bus EEPROM Application
When the PCI bus is reset and the serial-bus interface is detected, the PCIxx12 controller attempts to read
the subsystem identification and other register defaults from a serial EEPROM.
This format must be followed for the controller to load initializations from a serial EEPROM. All bit fields must
be considered when programming the EEPROM.
The serial EEPROM is addressed at slave address 1010 000b by the controller. All hardware address bits for
the EEPROM must be tied to the appropriate level to achieve this address. The serial EEPROM chip in the
sample application (Figure 311) assumes the 1010b high-address nibble. The lower three address bits are
terminal inputs to the chip, and the sample application shows these terminal inputs tied to GND.