
OHCI Registers
161
September 2005
SCPS110
8.10 GUID High Register
The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the
third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This
register initializes to 0000 0000h on a system (hardware) reset, which is an illegal GUID value. If a serial
EEPROM is detected, then the contents of this register are loaded through the serial EEPROM interface after
a GRST. At that point, the contents of this register cannot be changed. If no serial EEPROM is detected, then
the contents of this register are loaded by the BIOS. At that point, the contents of this register cannot be
changed. All bits in this register are reset by GRST only.
OHCI register offset:
24h
Register type:
Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
8.11 GUID Low Register
The GUID low register represents the lower quadlet in a 64-bit global unique ID (GUID) which maps to
chip_ID_lo in the Bus_Info_Block. This register initializes to 0000 0000h on a system (hardware) reset and
behaves identical to the GUID high register at OHCI offset 24h (see Section 8.10). All bits in this register are
reset by GRST only.
OHCI register offset:
28h
Register type:
Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
8.12 Configuration ROM Mapping Register
The configuration ROM mapping register contains the start address within system memory that maps to the
start address of 1394 configuration ROM for this node. See Table 88 for a complete description of the register
contents.
OHCI register offset:
34h
Register type:
Read/Write
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 88. Configuration ROM Mapping Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3110
configROMaddr
RW
If a quadlet read request to 1394 offset FFFF F000 0400h through offset FFFF F000 07FFh is
received, then the low-order 10 bits of the offset are added to this register to determine the host memory
address of the read request.
90
RSVD
R
Reserved. Bits 90 return 0s when read.