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| 型號(hào)： | SN2005118412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 74/271頁(yè) |
| 文件大小： | 3240K |
| 代理商： | SN2005118412ZHK |
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OHCI Controller Programming Model
149
September 2005
SCPS110
Table 720. PCI Miscellaneous Configuration Register Description (Continued)
2
DISABLE_
SCLKGATE
RW
When bit 2 is set to 1b, the internal SCLK runs identically with the chip input. This is a test feature
only and must be cleared to 0b (all applications).
1
DISABLE_
PCIGATE
RW
When bit 1 is set to 1b, the internal PCI clock runs identically with the chip input. This is a test feature
only and must be cleared to 0b (all applications).
0
KEEP_PCLK
RW
When bit 0 is set to 1b, the PCI clock is always kept running through the CLKRUN protocol. When
this bit is cleared, the PCI clock can be stopped using CLKRUN on MFUNC6.
This bit is cleared only by the assertion of GRST.
7.24 Link Enhancement Control Register
The link enhancement control register implements TI proprietary bits that are initialized by software or by a
serial EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22
(aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 8.16) is set
to 1b. See Table 721 for a complete description of the register contents.
Function 1 register offset: F4h
Register type:
Read/Write, Read-only
Default value:
0000 1000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
Table 721. Link Enhancement Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3116
RSVD
R
Reserved. Bits 3116 return 0000h when read.
15
dis_at_pipeline
RW
Disable AT pipelining. When bit 15 is set to 1b, out-of-order AT pipelining is disabled. The default value for
this bit is 0b.
14
RSVD
R
Reserved. Bit 14 defaults to 0b and must remain 0b for normal operation of the OHCI core.
1312
atx_thresh
RW
This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the controller
retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward operation.
00 = Threshold ~ 2K bytes resulting in a store-and-forward operation
01 = Threshold ~ 1.7K bytes (default)
10 = Threshold ~ 1K bytes
11 = Threshold ~ 512 bytes
These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte threshold is
optimal. Changing this value may increase or decrease the 1394 latency depending on the average PCI bus
latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds or
when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger than the AT
threshold, then the remaining data must be received before the AT FIFO is emptied; otherwise, an underrun
condition occurs, resulting in a packet error at the receiving node. As a result, the link then commences a
store-and-forward operation. It waits until it has the complete packet in the FIFO before retransmitting it on
the second attempt to ensure delivery.
An AT threshold of 2K results in a store-and-forward operation, which means that asynchronous data is not
transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 2K results in only
complete packets being transmitted.
Note that this controller always uses a store-and-forward operation when the asynchronous transmit retries
register at OHCI offset 08h (see Section 8.3) is cleared.
11
RSVD
R
Reserved. Bit 11 returns 0b when read.
10
enab_mpeg_ts
RW
Enable MPEG CIP timestamp enhancement. When bit 9 is set to 1b, the enhancement is enabled for MPEG
CIP transmit streams (FMT = 20h). The default value for this bit is 0b.
These bits are cleared only by the assertion of GRST.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SNA7412ZHK | PCMCIA BUS CONTROLLER, PBGA216 |
| SN260Q | LOCAL AREA NETWORK CONTROLLER, QCC40 |
| SN54128J | TTL/H/L SERIES, QUAD 2-INPUT NOR GATE, CDIP14 |
| SNJ54128W | TTL/H/L SERIES, QUAD 2-INPUT NOR GATE, CDFP14 |
| SN54132J | TTL/H/L SERIES, QUAD 2-INPUT NAND GATE, CDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN200512N | 制造商:Texas Instruments 功能描述: |
| SN200513N | 制造商:Texas Instruments 功能描述: |
| SN200515N | 制造商:Texas Instruments 功能描述: |
| SN200520N | 制造商:Texas Instruments 功能描述: |
| SN200530DR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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