
OHCI Registers
174
September 2005
SCPS110
8.27 Initial Bandwidth Available Register
The initial bandwidth available register value is loaded into the corresponding bus management CSR register
on a system (hardware) or software reset. See Table 819 for a complete description of the register contents.
OHCI register offset:
B0h
Register type:
Read-only, Read/Write
Default value:
0000 1333h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0
1
0
1
Table 819. Initial Bandwidth Available Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3113
RSVD
R
Reserved. Bits 3113 return 0s when read.
120
InitBWAvailable
RW
This field is reset to 1333h on a system (hardware) or software reset, and is not affected by a 1394
bus reset. The value of this field is loaded into the BANDWIDTH_AVAILABLE CSR register upon
a GRST, PRST, or a 1394 bus reset.
8.28 Initial Channels Available High Register
The initial channels available high register value is loaded into the corresponding bus management CSR
register on a system (hardware) or software reset. See Table 820 for a complete description of the register
contents.
OHCI register offset:
B4h
Register type:
Read/Write
Default value:
FFFF FFFFh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
1
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
1
Table 820. Initial Channels Available High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
310
InitChanAvailHi
RW
This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR
register upon a GRST, PRST, or a 1394 bus reset.