
OHCI Controller Programming Model
145
September 2005
SCPS110
7.19 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the controller related to PCI power
management. See Table 716 for a complete description of the register contents.
Function 1 register offset: 46h
Register type:
Read/Update, Read-only
Default value:
7E02h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0
Table 716. Power Management Capabilities Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_D3COLD
RU
PME support from D3cold. This bit can be set to 1b or cleared to 0b via bit 15 (PME_D3COLD) in the
PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see
Section 7.23). The PCI miscellaneous configuration register is loaded from ROM. When this bit is set
to 1b, it indicates that the controller is capable of generating a PME wake event from D3cold. This bit
state is dependent upon the VAUX implementation and may be configured by using bit 15
(PME_D3COLD) in the PCI miscellaneous configuration register (see Section 7.23).
1411
PME_SUPPORT
R
PME support. This 4-bit field indicates the power states from which the controller may assert PME. This
field returns a value of 1111b by default, indicating that PME may be asserted from the D3hot, D2, D1,
and D0 power states.
10
D2_SUPPORT
R
D2 support. Bit 10 is hardwired to 1b, indicating that the controller supports the D2 power state.
9
D1_SUPPORT
R
D1 support. Bit 9 is hardwired to 1b, indicating that the controller supports the D1 power state.
86
AUX_CURRENT
R
Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15
(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.
000b = Self-powered
001b = 55 mA (3.3-VAUX maximum current required)
5
DSI
R
Device-specific initialization. This bit returns 0b when read, indicating that the controller does not
require special initialization beyond the standard PCI configuration header before a generic class driver
is able to use it.
4
RSVD
R
Reserved. Bit 4 returns 0b when read.
3
PME_CLK
R
PME clock. This bit returns 0b when read, indicating that no host bus clock is required for the controller
to generate PME.
20
PM_VERSION
RU
Power-management version.
If bit 7 (PCI_PM_VERSION_CTRL) in the PCI miscellaneous configuration register (offset F0h, see
Section 7.23) is 0b, this field returns 010b indicating PCI Bus Power Management Interface
Specification (Revision 1.1) compatibility.
If the PCI_PM_VERSION_CTRL bit is 1b, this field returns 011b indicating PCI Bus Power
Management Interface Specification (Revision 1.2) compatibility.