
PC Card Controller Programming Model
98
September 2005
SCPS110
4.38 Device Control Register
The device control register is provided for PCI1130 compatibility. The interrupt mode select is programmed
through this register. The socket-capable force bits are also programmed through this register. See Table 417
for a complete description of the register contents.
PCI register offset:
92h (Function 0)
Register type:
Read-only, Read/Write
Default value:
66h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0
Table 417. Device Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
SKTPWR_LOCK
RW
Socket power lock bit. When this bit is set to 1b, software cannot power down the PC Card socket while
in D3. It may be necessary to lock socket power in order to support wake on LAN or RING if the
operating system is programmed to power down a socket when the CardBus controller is placed in the
D3 state.
6 §
3VCAPABLE
RW
3-V socket capable force bit.
0 = Not 3-V capable
1 = 3-V capable (default)
5
IO16R2
RW
Diagnostic bit. This bit defaults to 1b.
4
PCI_PM_
VERSION_CTL
R
PCI power management version control. This bit controls the value reported in the Version field of the
power management capabilities register of the CardBus function (PCI offset A2h, see Section 4.42).
0 = Version field reports 010b for PCI Bus Power Management Interface Specification
(Revision 1.1) compliance
1 = Version field reports 011b for PCI Bus Power Management Interface Specification
(Revision 1.2) compliance
3 §
TEST
RW
TI test bit. Write only 0b to this bit.
21 §
INTMODE
RW
Interrupt mode. These bits select the interrupt signaling mode. The interrupt mode bits are encoded:
00 = Parallel PCI interrupts only
01 = Reserved
10 = IRQ serialized interrupts and parallel PCI interrupts INTA, INTB, INTC, and INTD
11 = IRQ and PCI serialized interrupts (default)
0 §
RSVD
RW
Reserved. Bit 0 is reserved for test purposes. Only a 0b must be written to this bit.
This bit is cleared only by the assertion of GRST.
§ These bits are global in nature and must be accessed only through function 0.