
Features
1
September 2005
SCPS110
1
PCIxx12 Features
D PC Card Standard 8.1 Compliant
D PCI Bus Power Management Interface
Specification 1.1 Compliant
D Advanced Configuration and Power
Interface (ACPI) Specification 2.0
Compliant
D PCI Local Bus Specification Revision 2.3
Compliant
D Windows Logo Program Compliant
D PCI Bus Interface Specification for
PCI-to-CardBus Bridges
D Fully Compliant with Provisions of IEEE
Std 1394-1995 for a High-Performance
Serial Bus and IEEE Std 1394a-2000
D Fully Compliant with 1394 Open Host
Controller Interface Specification 1.1
D 1.5-V Core Logic and 3.3-V I/O Cells with
Internal Voltage Regulator to Generate
1.5-V Core VCC
D Universal PCI Interfaces Compatible with
3.3-V and 5-V PCI Signaling Environments
D Supports PC Card or CardBus with Hot
Insertion and Removal
D Supports 132-MBps Burst Transfers to
Maximize Data Throughput on Both the PCI
Bus and the CardBus
D Supports Serialized IRQ with PCI Interrupts
D Programmable Multifunction Terminals
D Many Interrupt Modes Supported
D Serial ROM Interface for Loading
Subsystem ID and Subsystem Vendor ID
D ExCA-Compatible Registers Are Mapped in
Memory or I/O Space
D Intel 82365SL-DF Register Compatible
D Supports Ring Indicate, SUSPEND, and PCI
CLKRUN Protocols
D Provides VGA/Palette Memory and I/O, and
Subtractive Decoding Options, LED Activity
Terminals
D Fully Interoperable with FireWireE and
i.LINK
E Implementations of IEEE Std 1394
D Compliant with Intel Mobile Power
Guideline 2000
D Full IEEE Std 1394a-2000 Support Includes:
Connection Debounce, Arbitrated Short
Reset, Multispeed Concatenation,
Arbitration Acceleration, Fly-By
Concatenation, and Port
Disable/Suspend/Resume
D Power-Down Features to Conserve Energy
in Battery-Powered Applications Include:
Automatic Device Power Down During
Suspend, PCI Power Management for
Link-Layer, and Inactive Ports Powered
Down, Ultralow-Power Sleep Mode
D Two IEEE Std 1394a-2000 Fully Compliant
Cable Ports at 100M Bits/s, 200M Bits/s,
and 400M Bits/s
D Cable Ports Monitor Line Conditions for
Active Connection to Remote Node
D Cable Power Presence Monitoring
D Separate Cable Bias (TPBIAS) for Each Port
D Physical Write Posting of up to Three
Outstanding Transactions
D PCI Burst Transfers and Deep FIFOs to
Tolerate Large Host Latency
D External Cycle Timer Control for
Customized Synchronization
D Extended Resume Signaling for
Compatibility with Legacy DV Components
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