
SD Host Controller Programming Model
221
September 2005
SCPS110
12.9 Subsystem Vendor Identification Register
The subsystem identification register, used for system and option card identification purposes, may be
required for certain operating systems. This read-only register is initialized through the EEPROM and can be
written through the subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register
are reset by GRST only.
Function 3 register offset: 2Ch
Register type:
Read/Update
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
12.10 Subsystem Identification Register
The subsystem identification register, used for system and option card identification purposes, may be
required for certain operating systems. This read-only register is initialized through the EEPROM and can be
written through the subsystem access register at PCI offset 8Ch (see Section 12.23). All bits in this register
are reset by GRST only.
Function 3 register offset: 2Eh
Register type:
Read/Update
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
12.11 Capabilities Pointer Register
The power-management capabilities pointer register provides a pointer into the PCI configuration header
where the power-management register block resides. Since the PCI power-management registers begin at
80h, this read-only register is hardwired to 80h.
Function 3 register offset: 34h
Register type:
Read-only
Default value:
80h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
1
0
12.12 Interrupt Line Register
The interrupt line register is programmed by the system and indicates to the software which interrupt line the
SD host controller has assigned to it. The default value of this register is FFh, indicating that an interrupt line
has not yet been assigned to the function.
Function 3 register offset: 3Ch
Register type:
Read/Write
Default value:
FFh
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
1