
PC Card Controller Programming Model
97
September 2005
SCPS110
4.37 Card Control Register
The card control register is provided for PCI1130 compatibility. The RI_OUT signal is enabled through this
register. See Table 416 for a complete description of the register contents.
PCI register offset:
91h
Register type:
Read-only, Read/Write
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
Table 416. Card Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
7 §
RIENB
RW
Ring indicate enable. When this bit is 1b, the RI_OUT output is enabled. This bit defaults to 0b.
63
RSVD
RW
These bits are reserved. Do not change the value of these bits.
2
AUD2MUX
RW
CardBus audio-to-MFUNC. When this bit is set, the CAUDIO CardBus signal must be routed through an
MFUNC terminal.
0 = CAUDIO set to CAUDPWM on MFUNC terminal (default)
1 = CAUDIO is not routed
1
SPKROUTEN
RW
When bit 1 is set, the SPKR terminal from the PC Card is enabled and is routed to tthe SPKROUT terminal.
The SPKROUT terminal drives data only when the SPKROUTEN bit is set. This bit is encoded as:
0 = SPKR to SPKROUT not enabled (default)
1 = SPKR to SPKROUT enabled
0
IFG
RW
Interrupt flag. This bit is the interrupt flag for 16-bit I/O PC Cards and for CardBus cards. This bit is set when
a functional interrupt is signaled from a PC Card interface. Write back a 1b to clear this bit.
0 = No PC Card functional interrupt detected (default)
1 = PC Card functional interrupt detected
This bit is cleared only by the assertion of GRST.
§ This bit is global in nature and must be accessed only through function 0.