
PC Card Controller Programming Model
95
September 2005
SCPS110
4.35 Multifunction Routing Status Register
The multifunction routing status register is used to configure the MFUNC6MFUNC0 terminals. These
terminals may be configured for various functions. This register is intended to be programmed once at
power-on initialization. The default value for this register can also be loaded through a serial EEPROM. See
Table 414 for a complete description of the register contents.
PCI register offset:
8Ch
Register type:
Read/Write, Read-only
Default value:
0100 1000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
1
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
Table 414. Multifunction Routing Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
3128
RSVD
R
Bits 3128 return 0h when read.
2724
MFUNC6
RW
Multifunction terminal 6 configuration. These bits control the internal signal mapped to the MFUNC6 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
1100 = IRQ12
0001 = CLKRUN
0101 = IRQ5
1001 = IRQ9
1101 = IRQ13
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
1110 = IRQ14
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1111 = IRQ15
2320
MFUNC5
RW
Multifunction terminal 5 configuration. These bits control the internal signal mapped to the MFUNC5 terminal
as follows:
0000 = GPI4
0100 = SC_DBG_RX
1000 = CAUDPWM
1100 = LEDA1
0001 = GPO4
0101 = IRQ5
1001 = RSVD
1101 = LED_SKT
0010 = PCGNT
0110 = RSVD
1010 = FM_LED
1110 = GPE
0011 = RSVD
0111 = RSVD
1011 = OHCI_LED
1111 = IRQ15
1916
MFUNC4
RW
Multifunction terminal 4 configuration. These bits control the internal signal mapped to the MFUNC4 terminal
as follows:
0000 = GPI3
0100 = IRQ4
1000 = CAUDPWM
1100 = RI_OUT
0001 = GPO3
0101 = SC_DBG_TX
1001 = IRQ9
1101 = LED_SKT
0010 = RSVD
0110 = RSVD
1010 = INTD
1110 = GPE
0011 = RSVD
0111 = RSVD
1011 = FM_LED
1111 = IRQ15
1512
MFUNC3
RW
Multifunction terminal 3 configuration. These bits control the internal signal mapped to the MFUNC3 terminal
as follows:
0000 = RSVD
0100 = IRQ4
1000 = IRQ8
1100 = IRQ12
0001 = IRQSER
0101 = IRQ5
1001 = IRQ9
1101 = IRQ13
0010 = IRQ2
0110 = IRQ6
1010 = IRQ10
1110 = IRQ14
0011 = IRQ3
0111 = IRQ7
1011 = IRQ11
1111 = IRQ15
118
MFUNC2
RW
Multifunction terminal 2 configuration. These bits control the internal signal mapped to the MFUNC2 terminal
as follows:
0000 = GPI2
0100 = RSVD
1000 = CAUDPWM
1100 = RI_OUT
0001 = GPO2
0101 = RSVD
1001 = FM_LED
1101 = TEST_MUX
0010 = PCREQ
0110 = RSVD
1010 = IRQ10
1110 = GPE
0011 = IRQ3
0111 = RSVD
1011 = INTC
1111 = IRQ7
These bits are cleared only by the assertion of GRST.