
PC Card Controller Programming Model
86
September 2005
SCPS110
4.23 Interrupt Line Register
The interrupt line register is a read/write register used by the host software. As part of the interrupt routing
procedure, the host software writes this register with the value of the system IRQ assigned to the function.
PCI register offset:
3Ch
Register type:
Read/Write
Default value:
FFh
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
1
4.24 Interrupt Pin Register
The value read from this register is function dependent. The default value for function 0 is 01h (INTA), the
default value for function 1 is 02h (INTB), the default value for function 2 is 01h (INTA), the default value for
function 3 is 01h (INTA), the default value for function 4 is 01h (INTA). The value also depends on the values
of bits 28, the tie-all bit (TIEALL), and 29, the interrupt tie bit (INTRTIE), in the system control register (PCI
offset 80h, see Section 4.29). The INTRTIE bit is compatible with previous TI CardBus controllers, and when
set to 1b, ties INTB to INTA internally. The TIEALL bit ties INTA, INTB, INTC, and INTD together internally.
The internal interrupt connections set by INTRTIE and TIEALL are communicated to host software through
this standard register interface. This read-only register is described for all PCIxx12 functions in Table 46.
PCI register offset:
3Dh
Register type:
Read-only
Default value:
01h (function 0), 02h (function 1), 01h (function 2), 01h (function 3), 01h (function 4)
PCI function 0
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
1
PCI function 1
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
1
PCI function 2
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
X
PCI function 3
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
X
PCI function 4
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
X
Table 46. Interrupt Pin Register Cross Reference
INTRTIE BIT
(BIT 29,
OFFSET 80H)
TIEALL BIT
(BIT 28,
OFFSET 80H)
INTPIN
FUNCTION 0
(CARDBUS)
INTPIN
FUNCTION 1
(1394 OHCI)
INTPIN
FUNCTION 2
(FLASH MEDIA)
INTPIN
FUNCTION 3
(SD HOST)
INTPIN
FUNCTION 4
(SMART CARD)
0
01h (INTA)
02h (INTB)
Determined by bits 65
(INT_SEL) in the flash
media general control
Determined by bits 65
(INT_SEL) in the SD
host general control
Determined by bits 65
(INT_SEL) in the
Smart Card general
1
0
01h (INTA)
media general control
register (see
Section 11.21)
host general control
register (see
Section 12.22)
Smart Card general
control register (see
Section 13.22)
X
1
01h (INTA)