
OHCI Controller Programming Model
141
September 2005
SCPS110
7.11 CardBus CIS Pointer Register
The internal CARDBUS input to the 1394 OHCI core is tied high such that this register returns 0000 0000h
when read.
Function 1 register offset: 28h
Register type:
Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
7.12 Subsystem Identification Register
The subsystem identification register is used for system and option card identification purposes. This register
can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h
in the PCI configuration space (see Section 7.25). See Table 710 for a complete description of the register
contents.
Function 1 register offset: 2Ch
Register type:
Read/Update
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 710. Subsystem Identification Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3116
OHCI_SSID
RU
Subsystem device ID. This field indicates the subsystem device ID.
150
OHCI_SSVID
RU
Subsystem vendor ID. This field indicates the subsystem vendor ID.
These bits are cleared only by the assertion of GRST.
7.13 Power Management Capabilities Pointer Register
The power management capabilities pointer register provides a pointer into the PCI configuration header
where the power-management register block resides. The configuration header doublewords at offsets 44h
and 48h provide the power-management registers. This register is read-only and returns 44h when read.
Function 1 register offset: 34h
Register type:
Read-only
Default value:
44h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0