
Principles of Operation
45
September 2005
SCPS110
3.4.2 Device Resets
The following are the requirements for proper reset of the PCIxx12 controller:
1.
GRST and PRST must both be asserted at power on.
2.
GRST must be asserted for at least 2 ms at power on.
3.
PRST must be deasserted either at the same time or after GRST is asserted.
4.
PCLK must be stable for 100
s before PRST is deasserted.
VCC
GRST
PRST
PCLK
> 2 ms
> 0 ns
> 100
ms
Figure 33. PCI Reset Requirement
3.4.3 Serial EEPROM I2C Bus
The PCIxx12 controller offers many choices for modes of operation, and these choices are selected by
programming several configuration registers. For system board applications, these registers are normally
programmed through the BIOS routine. For add-in card and docking-station/port-replicator applications, the
controller provides a two-wire inter-integrated circuit (IIC or I2C) serial bus for use with an external serial
EEPROM.
The controller is always the bus master, and the EEPROM is always the slave. Either device can drive the bus
low, but neither device drives the bus high. The high level is achieved through the use of pullup resistors on
the SCL and SDA signal lines. The controller is always the source of the clock signal, SCL.
System designers who wish to load register values with a serial EEPROM must use pullup resistors on the
SCL and SDA terminals. If the controller detects a logic-high level on the SCL terminal at the end of GRST,
then it initiates incremental reads from the external EEPROM. Any size serial EEPROM up to the I2C limit of
16 Kbits can be used, but only the first 96 bytes (from offset 00h to offset 5Fh) are required to configure the
controller. Figure 33 shows a serial EEPROM application.