參數(shù)資料
型號(hào): SN2005118412ZHK
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): 總線(xiàn)控制器
英文描述: PCMCIA BUS CONTROLLER, PBGA216
封裝: GREEN, PLASTIC, MICRO BGA-216
文件頁(yè)數(shù): 20/271頁(yè)
文件大小: 3240K
代理商: SN2005118412ZHK
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)
PC Card Controller Programming Model
100
September 2005
SCPS110
4.42 Power Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PC Card function
related to power management. The CardBus bridge function supports D0, D1, D2, and D3 power states.
Default register value is FE12h for operation in accordance with PCI Bus Power Management Interface
Specification revision 1.1. See Table 419 for a complete description of the register contents.
PCI register offset:
A2h (Function 0)
Register type:
Read-only, Read/Write
Default value:
FE12h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
1
0
1
0
1
0
Table 419. Power Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
This 5-bit field indicates the power states from which the controller function can assert PME. A 0b for any
bit indicates that the function cannot assert the PME signal while in that power state. These 5 bits return
11111b when read. Each of these bits is described below:
15
PME support
RW
Bit 15 defaults to a 1b indicating the PME signal can be asserted from the D3cold state. This bit is
read/write because wake-up support from D3cold is contingent on the system providing an auxiliary power
source to the VCC terminals. If the system designer chooses not to provide an auxiliary power source to
the VCC terminals for D3cold wake-up support, then BIOS must write a 0b to this bit.
1411
R
Bit 14 contains the value 1b to indicate that the PME signal can be asserted from the D3hot state.
Bit 13 contains the value 1b to indicate that the PME signal can be asserted from the D2 state.
Bit 12 contains the value 1b to indicate that the PME signal can be asserted from the D1 state.
Bit 11 contains the value 1b to indicate that the PME signal can be asserted from the D0 state.
10
D2_Support
R
This bit returns a 1b when read, indicating that the function supports the D2 device power state.
9
D1_Support
R
This bit returns a 1b when read, indicating that the function supports the D1 device power state.
86
RSVD
R
Reserved. These bits return 000b when read.
5
DSI
R
Device-specific initialization. This bit returns 0b when read.
4
AUX_PWR
R
Auxiliary power source. This bit is meaningful only if bit 15 (D3cold supporting PME) is set. When this bit
is set, it indicates that support for PME in D3cold requires auxiliary power supplied by the system by way
of a proprietary delivery vehicle.
A 0b in this bit field indicates that the function supplies its own auxiliary power source.
If the function does not support PME while in the D3cold state (bit 15 = 0), then this field must always return
0b.
3
PMECLK
R
When this bit is 1b, it indicates that the function relies on the presence of the PCI clock for PME operation.
When this bit is 0b, it indicates that no PCI clock is required for the function to generate PME.
Functions that do not support PME generation in any state must return 0b for this bit.
20
Version
R
Power management version.
If bit 4 (PCI_PM_VERSION_CTRL) in the device control register (PCI offset 92h, see Section 4.38) is 0b,
this field returns 010b indicating PCI Bus Power Management Interface Specification (Revision 1.1)
compatibility.
If bit 4 (PCI_PM_VERSION_CTRL) in the device control register is 1b, this field returns 011b indicating
PCI Bus Power Management Interface Specification (Revision 1.2) compatibility.
This bit is cleared only by the assertion of GRST.
相關(guān)PDF資料
PDF描述
SNA7412ZHK PCMCIA BUS CONTROLLER, PBGA216
SN260Q LOCAL AREA NETWORK CONTROLLER, QCC40
SN54128J TTL/H/L SERIES, QUAD 2-INPUT NOR GATE, CDIP14
SNJ54128W TTL/H/L SERIES, QUAD 2-INPUT NOR GATE, CDFP14
SN54132J TTL/H/L SERIES, QUAD 2-INPUT NAND GATE, CDIP14
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SN200512N 制造商:Texas Instruments 功能描述:
SN200513N 制造商:Texas Instruments 功能描述:
SN200515N 制造商:Texas Instruments 功能描述:
SN200520N 制造商:Texas Instruments 功能描述:
SN200530DR 制造商:Rochester Electronics LLC 功能描述:- Bulk