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| 型號(hào)： | SN2005118412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 117/271頁(yè) |
| 文件大小： | 3240K |
| 代理商： | SN2005118412ZHK |
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OHCI Registers
187
September 2005
SCPS110
8.42 Isochronous Transmit Context Control Register
The isochronous transmit context control set/clear register controls options, state, and status for the
isochronous transmit DMA contexts. The n value in the following register addresses indicates the context
number (n = 0, 1, 2, 3,
…, 7). See Table 833 for a complete description of the register contents.
OHCI register offset:
200h + (16 * n)
set register
204h + (16 * n)
clear register
Register type:
Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update,
Read-only
Default value:
XXXX X0XXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
X
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
X
0
X
Table 833. Isochronous Transmit Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
cycleMatchEnable
RSCU
When bit 31 is set to 1b, processing occurs such that the packet described by the context first
descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field
(bits 3016). The cycleMatch field (bits 3016) must match the low-order two bits of cycleSeconds
and the 13-bit cycleCount field in the cycle start packet that is sent or received immediately before
isochronous transmission begins. Since the isochronous transmit DMA controller may work ahead,
the processing of the first descriptor block may begin slightly in advance of the actual cycle in which
the first packet is transmitted.
The effects of this bit, however, are impacted by the values of other bits in this register and are
explained in the 1394 Open Host Controller Interface Specification. Once the context has become
active, hardware clears this bit.
3016
cycleMatch
RSC
This field contains a 15-bit value, corresponding to the low-order two bits of the isochronous cycle
timer register at OHCI offset F0h (see Section 8.34) cycleSeconds field (bits 3125) and the
cycleCount field (bits 2412). If bit 31 (cycleMatchEnable) is set to 1b, then this isochronous transmit
DMA context becomes enabled for transmits when the low-order two bits of the isochronous cycle
timer register at OHCI offset F0h cycleSeconds field (bits 3125) and the cycleCount field
(bits 2412) value equal this field (cycleMatch) value.
15
run
RSC
Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared by software
to stop descriptor processing. The controller changes this bit only on a system (hardware) or software
reset.
1413
RSVD
R
Reserved. Bits 14 and 13 return 00b when read.
12
wake
RSU
Software sets bit 12 to 1b to cause the controller to continue or resume descriptor processing. The
controller clears this bit on every descriptor fetch.
11
dead
RU
The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when software clears
bit 15 (run) to 0b.
10
active
RU
The controller sets bit 10 to 1b when it is processing descriptors.
98
RSVD
R
Reserved. Bits 9 and 8 return 00b when read.
75
spd
RU
This field in not meaningful for isochronous transmit contexts.
40
event code
RU
Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible values are:
ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
On an overflow for each running context, the isochronous transmit DMA supports up to 7 cycle skips, when the following are true:
1. Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1b.
2. Bits 40 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout.
3. Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 8.21) is set to 1b.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SNA7412ZHK | PCMCIA BUS CONTROLLER, PBGA216 |
| SN260Q | LOCAL AREA NETWORK CONTROLLER, QCC40 |
| SN54128J | TTL/H/L SERIES, QUAD 2-INPUT NOR GATE, CDIP14 |
| SNJ54128W | TTL/H/L SERIES, QUAD 2-INPUT NOR GATE, CDFP14 |
| SN54132J | TTL/H/L SERIES, QUAD 2-INPUT NAND GATE, CDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN200512N | 制造商:Texas Instruments 功能描述: |
| SN200513N | 制造商:Texas Instruments 功能描述: |
| SN200515N | 制造商:Texas Instruments 功能描述: |
| SN200520N | 制造商:Texas Instruments 功能描述: |
| SN200530DR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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