
OHCI Registers
162
September 2005
SCPS110
8.13 Posted Write Address Low Register
The posted write address low register communicates error information if a write request is posted and an error
occurs while the posted data packet is being written. See Table 89 for a complete description of the register
contents.
OHCI register offset:
38h
Register type:
Read/Update
Default value:
XXXX XXXXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
X
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
X
Table 89. Posted Write Address Low Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
310
offsetLo
RU
The lower 32 bits of the 1394 destination offset of the write request that failed.
8.14 Posted Write Address High Register
The posted write address high register communicates error information if a write request is posted and an error
occurs while writing the posted data packet. See Table 810 for a complete description of the register
contents.
OHCI register offset:
3Ch
Register type:
Read/Update
Default value:
XXXX XXXXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
X
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
X
Table 810. Posted Write Address High Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3116
sourceID
RU
This field is the 10-bit bus number (bits 3122) and 6-bit node number (bits 2116) of the node that
issued the write request that failed.
150
offsetHi
RU
The upper 16 bits of the 1394 destination offset of the write request that failed.
8.15 Vendor ID Register
The vendor ID register holds the company ID of an organization that specifies any vendor-unique registers.
The controller implements Texas Instruments unique behavior with regards to OHCI. Thus, this register is
read-only and returns 0108 0028h when read.
OHCI register offset:
40h
Register type:
Read-only
Default value:
0108 0028h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
1
0
1
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0