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參數(shù)資料
| 型號(hào)： | SN2005118412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 6/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SN2005118412ZHK |
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PC Card Controller Programming Model
87
September 2005
SCPS110
4.25 Bridge Control Register
The bridge control register provides control over various PCIxx12 bridging functions. Some bits in this register
are global in nature and must be accessed only through function 0. See Table 47 for a complete description
of the register contents.
PCI register offset:
3Eh (Function 0)
Register type:
Read-only, Read/Write
Default value:
0340h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0
Table 47. Bridge Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
1511
RSVD
R
These bits return 00000b when read.
10
POSTEN
RW
Write posting enable. Enables write posting to and from the CardBus socket. Write posting enables the
posting of write data on burst cycles. Operating with write posting disabled impairs performance on burst
cycles. Note that burst write data can be posted, but various write transactions may not.
9
PREFETCH1
RW
Memory window 1 type. This bit specifies whether or not memory window 1 is prefetchable. This bit is
encoded as:
0 = Memory window 1 is nonprefetchable
1 = Memory window 1 is prefetchable (default)
8
PREFETCH0
RW
Memory window 0 type. This bit specifies whether or not memory window 0 is prefetchable. This bit is
encoded as:
0 = Memory window 0 is nonprefetchable
1 = Memory window 0 is prefetchable (default)
7
INTR
RW
PCI interrupt IREQ routing enable. This bit selects whether PC Card functional interrupts are routed to
PCI interrupts or to the IRQ specified in the ExCA registers.
0 = Functional interrupts are routed to PCI interrupts (default).
1 = Functional interrupts are routed by ExCA registers.
6
CRST
RW
CardBus reset. When this bit is set, the CRST signal is asserted on the CardBus interface. The CRST
signal can also be asserted by passing a PRST assertion to CardBus.
0 = CRST is deasserted
1 = CRST is asserted (default)
This bit is not cleared by the assertion of PRST. It is only cleared by the assertion of GRST.
5
MABTMODE
RW
Master abort mode. This bit controls how the controller responds to a master abort when the controller is
an initiator on the CardBus interface.
0 = Master aborts not reported (default)
1 = Signal target abort on PCI and signal SERR, if enabled
4
RSVD
R
This bit returns 0b when read.
3
VGAEN
RW
VGA enable. This bit affects how the controller responds to VGA addresses. When this bit is set, accesses
to VGA addresses are forwarded.
2
ISAEN
RW
ISA mode enable. This bit affects how the controller passes I/O cycles within the 64-Kbyte ISA range.
When this bit is set, the controller does not forward the last 768 bytes of each 1K I/O range to CardBus.
1
CSERREN
RW
CSERR enable. This bit controls the response of the controller to CSERR signals on the CardBus bus.
0 = CSERR is not forwarded to PCI SERR (default)
1 = CSERR is forwarded to PCI SERR
0
CPERREN
RW
CardBus parity error response enable. This bit controls the response of the controller to CardBus parity
errors.
0 = CardBus parity errors are ignored (default)
1 = CardBus parity errors are reported using CPERR
One or more bits in this register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then this bit is cleared by the assertion of PRST or GRST.
相關(guān)PDF資料 |
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| SNA7412ZHK | PCMCIA BUS CONTROLLER, PBGA216 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN200512N | 制造商:Texas Instruments 功能描述: |
| SN200513N | 制造商:Texas Instruments 功能描述: |
| SN200515N | 制造商:Texas Instruments 功能描述: |
| SN200520N | 制造商:Texas Instruments 功能描述: |
| SN200530DR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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