
PC Card Controller Programming Model
83
September 2005
SCPS110
4.16 CardBus Bus Number Register
The CardBus bus number register is programmed by the host system to indicate the bus number of the
CardBus bus to which the controller is connected. The controller uses this register in conjunction with the PCI
bus number and subordinate bus number registers to determine when to forward PCI configuration cycles to
its secondary buses. This register is separate for each controller function.
PCI register offset:
19h
Register type:
Read/Write
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
4.17 Subordinate Bus Number Register
The subordinate bus number register is programmed by the host system to indicate the highest numbered bus
below the CardBus bus. The controller uses this register in conjunction with the PCI bus number and CardBus
bus number registers to determine when to forward PCI configuration cycles to its secondary buses.
PCI register offset:
1Ah
Register type:
Read/Write
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
4.18 CardBus Latency Timer Register
The CardBus latency timer register is programmed by the host system to specify the latency timer for the
CardBus interface, in units of CCLK cycles. When the controller is a CardBus initiator and asserts CFRAME,
the CardBus latency timer begins counting. If the latency timer expires before the PCIxx12 transaction has
terminated, then the controller terminates the transaction at the end of the next data phase. A recommended
minimum value for this register of 20h allows most transactions to be completed.
PCI register offset:
1Bh (Function 0)
Register type:
Read/Write
Default value:
00h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0