
Smart Card Controller Programming Model
237
September 2005
SCPS110
13.18 Power-Management Capabilities Register
The power-management capabilities register indicates the capabilities of the Smart Card controller related to
PCI power management. See Table 1311 for a complete description of the register contents.
Function 4 register offset: 46h
Register type:
Read/Update, Read-only
Default value:
7E02h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
1
0
Table 1311. Power-Management Capabilities Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_D3COLD
RU
PME support from D3cold. This bit can be set to 1b or cleared to 0b via bit 4 (D3_COLD) in the general
control register at offset 4Ch in the PCI configuration space (see Section 13.22). When this bit is set
to 1b, it indicates that the controller is capable of generating a PME wake event from D3cold. This bit
state is dependent upon the VAUX implementation and may be configured by using bit 4 (D3_COLD)
in the general control register (see Section 13.22).
14
PME_D3HOT
R
PME support. This 4-bit field indicates the power states from which the Smart Card interface may assert
13
PME_D2
R
PME support. This 4-bit field indicates the power states from which the Smart Card interface may assert
PME. This field returns a value of 1111b by default, indicating that PME may be asserted from the D3hot,
12
PME_D1
R
PME. This field returns a value of 1111b by default, indicating that PME may be asserted from the D3hot,
D2, D1, and D0 power states.
11
PME_D0
R
D2, D1, and D0 power states.
10
D2_SUPPORT
R
D2 support. Bit 10 is hardwired to 1b, indicating that the Smart Card controller supports the D2 power
state.
9
D1_SUPPORT
R
D1 support. Bit 9 is hardwired to 1b, indicating that the Smart Card controller supports the D1 power
state.
86
AUX_CURRENT
R
Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15
(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.
000b = Self-powered
001b = 55 mA (3.3-VAUX maximum current required)
5
DSI
R
Device-specific initialization. This function requires device-specific initialization.
4
RSVD
R
Reserved. Bit 4 returns 0b when read.
3
PME_CLK
R
PME clock. This bit returns 0b when read, indicating that the PCI clock is not required for the Smart
Card controller to generate PME.
20
PM_VERSION
R
Power-management version.
If bit 7 (PCI_PM_VERSION_CTRL) in the general control register (offset 4Ch, see Section 13.22) is
0b, this field returns 010b indicating PCI Bus Power Management Interface Specification
(Revision 1.1) compatibility.
If the PCI_PM_VERSION_CTRL bit is 1b, this field returns 011b indicating PCI Bus Power
Management Interface Specification (Revision 1.2) compatibility.