
CardBus Socket Registers (Function 0)
129
September 2005
SCPS110
6.3
Socket Present State Register
This register reports information about the socket interface. Writes to the socket force event register (offset
0Ch, see Section 6.4), as well as general socket interface status, are reflected here. Information about PC
Card VCC support and card type is only updated at each insertion. Also note that the PCIxx12 controller uses
the CCD1 and CCD2 signals during card identification, and changes on these signals during this operation
are not reflected in this register.
CardBus register offset:
CardBus Socket Address + 08h
Register type:
Read-only
Default value:
3000 00XXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
1
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
X
0
X
Table 64. Socket Present State Register Description
BIT
SIGNAL
TYPE
FUNCTION
31
YVSOCKET
R
YV socket. This bit indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The
controller does not support Y.Y-V VCC; therefore, this bit is always reset unless overridden by the socket
force event register (offset 0Ch, see Section 6.4). This bit defaults to 0b.
30
XVSOCKET
R
XV socket. This bit indicates whether or not the socket can supply VCC = X.X V to PC Cards. The
controller does not support X.X-V VCC; therefore, this bit is always reset unless overridden by the
socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0b.
29
3VSOCKET
R
3-V socket. This bit indicates whether or not the socket can supply VCC = 3.3 Vdc to PC Cards. The
controller does support 3.3-V VCC; therefore, this bit is always set unless overridden by the socket force
event register (offset 0Ch, see Section 6.4).
28
5VSOCKET
R
5-V socket. This bit indicates whether or not the socket can supply VCC = 5 Vdc to PC Cards. The
PCI712 controller does support 5-V VCC; therefore, this bit is always set unless overridden by bit 6 of
the device control register (PCI offset 92h, see Section 4.38).
2714
RSVD
R
These bits return 0s when read.
13
YVCARD
R
YV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y Vdc.
This bit can be set by writing a 1b to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
12
XVCARD
R
XV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = X.X Vdc.
This bit can be set by writing a 1b to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
11
3VCARD
R
3-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 Vdc.
This bit can be set by writing a 1b to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
10
5VCARD
R
5-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 5 Vdc.
This bit can be set by writing a 1b to the corresponding bit in the socket force event register (offset 0Ch,
see Section 6.4).
9
BADVCCREQ
R
Bad VCC request. This bit indicates that the host software has requested that the socket be powered
at an invalid voltage.
0 = Normal operation (default)
1 = Invalid VCC request by host software
8
DATALOST
R
Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle
did not terminate properly or because write data still resides in the controller.
0 = Normal operation (default)
1 = Potential data loss due to card removal
One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not
enabled, then these bits are cleared by the assertion of PRST or GRST.