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| 型號(hào)： | SN2005118412ZHK |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類(lèi)： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PBGA216 |
| 封裝： | GREEN, PLASTIC, MICRO BGA-216 |
| 文件頁(yè)數(shù)： | 118/271頁(yè) |
| 文件大?。?/td> | 3240K |
| 代理商： | SN2005118412ZHK |
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OHCI Registers
188
September 2005
SCPS110
8.43 Isochronous Transmit Context Command Pointer Register
The isochronous transmit context command pointer register contains a pointer to the address of the first
descriptor block that the controller accesses when software enables an isochronous transmit context by
setting bit 15 (run) in the isochronous transmit context control register (see Section 8.42) to 1b. The
isochronous transmit DMA context command pointer can be read when a context is active. The n value in the
following register addresses indicates the context number (n = 0, 1, 2, 3,
…, 7).
OHCI register offset:
20Ch + (16 * n)
Register type:
Read-only
Default value:
XXXX XXXXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
X
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
X
8.44 Isochronous Receive Context Control Register
The isochronous receive context control set/clear register controls options, state, and status for the
isochronous receive DMA contexts. The n value in the following register addresses indicates the context
number (n = 0, 1, 2, 3). See Table 834 for a complete description of the register contents.
OHCI register offset:
400h + (32 * n)
set register
404h + (32 * n)
clear register
Register type:
Read/Set/Clear/Update, Read/Set/Clear, Read/Set/Update, Read/Update,
Read-only
Default value:
XX00 X0XXh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
X
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
X
0
X
Table 834. Isochronous Receive Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31
bufferFill
RSC
When bit 31 is set to 1b, received packets are placed back-to-back to completely fill each receive
buffer. When this bit is cleared, each received packet is placed in a single buffer. If bit 28
(multiChanMode) is set to 1b, then this bit must also be set to 1b. The value of this bit must not be
changed while bit 10 (active) or bit 15 (run) is set to 1b.
30
isochHeader
RSC
When bit 30 is set to 1b, received isochronous packets include the complete 4-byte isochronous
packet header seen by the link layer. The end of the packet is marked with a xferStatus in the first
doublet, and a 16-bit timeStamp indicating the time of the most recently received (or sent) cycleStart
packet.
When this bit is cleared, the packet header is stripped from received isochronous packets. The
packet header, if received, immediately precedes the packet payload. The value of this bit must not
be changed while bit 10 (active) or bit 15 (run) is set to 1b.
29
cycleMatchEnable
RSCU
When bit 29 is set to 1b and the 13-bit cycleMatch field (bits 2412) in the isochronous receive
context match register (See Section 8.46) matches the 13-bit cycleCount field in the cycleStart
packet, the context begins running. The effects of this bit, however, are impacted by the values of
other bits in this register. Once the context has become active, hardware clears this bit. The value
of this bit must not be changed while bit 10 (active) or bit 15 (run) is set to 1b.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SNA7412ZHK | PCMCIA BUS CONTROLLER, PBGA216 |
| SN260Q | LOCAL AREA NETWORK CONTROLLER, QCC40 |
| SN54128J | TTL/H/L SERIES, QUAD 2-INPUT NOR GATE, CDIP14 |
| SNJ54128W | TTL/H/L SERIES, QUAD 2-INPUT NOR GATE, CDFP14 |
| SN54132J | TTL/H/L SERIES, QUAD 2-INPUT NAND GATE, CDIP14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN200512N | 制造商:Texas Instruments 功能描述: |
| SN200513N | 制造商:Texas Instruments 功能描述: |
| SN200515N | 制造商:Texas Instruments 功能描述: |
| SN200520N | 制造商:Texas Instruments 功能描述: |
| SN200530DR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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