
PC Card Controller Programming Model
88
September 2005
SCPS110
4.26 Subsystem Vendor ID Register
The subsystem vendor ID register, used for system and option card identification purposes, may be required
for certain operating systems. This register is read-only or read/write, depending on the setting of bit 5
(SUBSYSRW) in the system control register (PCI offset 80h, See Section 4.29). When bit 5 is 0b, this register
is read/write; when bit 5 is 1b, this register is read-only. The default mode is read-only. All bits in this register
are reset by GRST only.
PCI register offset:
40h (Function 0)
Register type:
Read-only, (Read/Write when bit 5 in the system control register is 0)
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
4.27 Subsystem ID Register
The subsystem ID register, used for system and option card identification purposes, may be required for
certain operating systems. This register is read-only or read/write, depending on the setting of bit 5
(SUBSYSRW) in the system control register (PCI offset 80h, see Section 4.29). When bit 5 is 0b, this register
is read/write; when bit 5 is 1b, this register is read-only. The default mode is read-only. All bits in this register
are reset by GRST only.
If an EEPROM is present, then the subsystem ID and subsystem vendor ID is loaded from the EEPROM after
a reset.
PCI register offset:
42h (Function 0)
Register type:
Read-only, (Read/Write when bit 5 in the system control register is 0)
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
4.28 PC Card 16-Bit I/F Legacy-Mode Base-Address Register
The controller supports the index/data scheme of accessing the ExCA registers, which is mapped by this
register. An address written to this register is the address for the index register and the address+1 is the data
address. Using this access method, applications requiring index/data ExCA access can be supported. The
base address can be mapped anywhere in 32-bit I/O space on a word boundary; hence, bit 0 is read-only,
returning 1b when read. As specified in the PCI to PCMCIA CardBus Bridge Register Description specification.
See the ExCA register set description in Section 5 for register offsets. All bits in this register are reset by GRST
only.
PCI register offset:
44h (Function 0)
Register type:
Read-only, Read/Write
Default value:
0000 0001h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1