
Flash Media Controller Programming Model
207
September 2005
SCPS110
11.7 Header Type and BIST Register
The header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and
no built-in self-test. See Table 116 for a complete description of the register contents.
Function 2 offset:
0Eh
Register type:
Read-only
Default value:
0080h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
1
0
Table 116. Header Type and BIST Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
158
BIST
R
Built-in self-test. The flash media controller does not include a BIST; therefore, this field returns 00h
when read.
70
HEADER_TYPE
R
PCI header type. The flash media controller includes the standard PCI header. Bit 7 indicates if the flash
media is a multifunction device.
11.8 Flash Media Base Address Register
The flash media base address register specifies the base address of the memory-mapped interface registers.
Since the implementation of the flash media controller core in the controller contains 2 sockets, the size of the
base address register is 4096 bytes. See Table 117 for a complete description of the register contents.
Function 2 offset:
10h
Register type:
Read/Write, Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
Table 117. Flash Media Base Address Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
3113
BAR
RW
Base address. This field specifies the upper bits of the 32-bit starting base address.
124
RSVD
R
Reserved. Bits 124 return 0s when read to indicate that the size of the base address is 8192 bytes.
3
PREFETCHABLE
R
Prefetchable. Since this base address is not prefetchable, bit 3 returns 0b when read.
21
RSVD
R
Reserved. Bits 21 return 00b when read.
0
MEM_INDICATOR
R
Memory space indicator. Bit 0 is hardwired to 0b to indicate that the base address maps into memory
space.
11.9 Subsystem Vendor Identification Register
The subsystem identification register, used for system and option card identification purposes, may be
required for certain operating systems. This read-only register is initialized through the EEPROM and can be
written through the subsystem access register at PCI offset 50h (see Section 11.22). All bits in this register
are reset by GRST only.
Function 2 offset:
2Ch
Register type:
Read/Update
Default value:
0000h
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0